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drm/omap: omap_display_timings: Use display_flags for h/vsync level 

In preparation to move the stack to use the generic videmode struct for
display timing information use display_flags for h/vsync level.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
This commit is contained in:
Peter Ujfalusi 2016-09-22 14:06:57 +03:00 committed by Tomi Valkeinen
parent 3b592939b7
commit 6b44cd2748
18 changed files with 52 additions and 83 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/gpu/drm/omapdrm/displays/connector-analog-tv.c
View File

@ -40,7 +40,8 @@ static const struct omap_video_timings tvc_pal_timings = {
.vfront_porch = 5, .vfront_porch = 5,
.vback_porch = 41, .vback_porch = 41,
.flags = DISPLAY_FLAGS_INTERLACED, .flags = DISPLAY_FLAGS_INTERLACED | DISPLAY_FLAGS_HSYNC_LOW |
DISPLAY_FLAGS_VSYNC_LOW,
}; };
static const struct of_device_id tvc_of_match[]; static const struct of_device_id tvc_of_match[];

4
drivers/gpu/drm/omapdrm/displays/connector-dvi.c
View File

@ -33,11 +33,11 @@ static const struct omap_video_timings dvic_default_timings = {
.vsync_len = 4, .vsync_len = 4,
.vback_porch = 7, .vback_porch = 7,
.vsync_level = OMAPDSS_SIG_ACTIVE_HIGH,
.hsync_level = OMAPDSS_SIG_ACTIVE_HIGH,
.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE, .data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
.de_level = OMAPDSS_SIG_ACTIVE_HIGH, .de_level = OMAPDSS_SIG_ACTIVE_HIGH,
.sync_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE, .sync_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE,
.flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH,
}; };
struct panel_drv_data { struct panel_drv_data {

3
drivers/gpu/drm/omapdrm/displays/connector-hdmi.c
View File

@ -32,8 +32,7 @@ static const struct omap_video_timings hdmic_default_timings = {
.vfront_porch = 11, .vfront_porch = 11,
.vback_porch = 31, .vback_porch = 31,
.vsync_level = OMAPDSS_SIG_ACTIVE_LOW, .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
.hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
}; };
struct panel_drv_data { struct panel_drv_data {

4
drivers/gpu/drm/omapdrm/displays/panel-lgphilips-lb035q02.c
View File

@ -33,11 +33,11 @@ static struct omap_video_timings lb035q02_timings = {
.vfront_porch = 4, .vfront_porch = 4,
.vback_porch = 18, .vback_porch = 18,
.vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
.hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE, .data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
.de_level = OMAPDSS_SIG_ACTIVE_HIGH, .de_level = OMAPDSS_SIG_ACTIVE_HIGH,
.sync_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE, .sync_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE,
.flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
}; };
struct panel_drv_data { struct panel_drv_data {

4
drivers/gpu/drm/omapdrm/displays/panel-nec-nl8048hl11.c
View File

@ -76,11 +76,11 @@ static const struct omap_video_timings nec_8048_panel_timings = {
.vsync_len = 1, .vsync_len = 1,
.vback_porch = 4, .vback_porch = 4,
.vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
.hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE, .data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
.de_level = OMAPDSS_SIG_ACTIVE_HIGH, .de_level = OMAPDSS_SIG_ACTIVE_HIGH,
.sync_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE, .sync_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
.flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
}; };
#define to_panel_data(p) container_of(p, struct panel_drv_data, dssdev) #define to_panel_data(p) container_of(p, struct panel_drv_data, dssdev)

4
drivers/gpu/drm/omapdrm/displays/panel-sharp-ls037v7dw01.c
View File

@ -49,11 +49,11 @@ static const struct omap_video_timings sharp_ls_timings = {
.vfront_porch = 1, .vfront_porch = 1,
.vback_porch = 1, .vback_porch = 1,
.vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
.hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE, .data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
.de_level = OMAPDSS_SIG_ACTIVE_HIGH, .de_level = OMAPDSS_SIG_ACTIVE_HIGH,
.sync_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE, .sync_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE,
.flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
}; };
#define to_panel_data(p) container_of(p, struct panel_drv_data, dssdev) #define to_panel_data(p) container_of(p, struct panel_drv_data, dssdev)

5
drivers/gpu/drm/omapdrm/displays/panel-sony-acx565akm.c
View File

@ -103,12 +103,11 @@ static const struct omap_video_timings acx565akm_panel_timings = {
.vsync_len = 3, .vsync_len = 3,
.vback_porch = 4, .vback_porch = 4,
.vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
.hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE, .data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
.de_level = OMAPDSS_SIG_ACTIVE_HIGH, .de_level = OMAPDSS_SIG_ACTIVE_HIGH,
.sync_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE, .sync_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE,
.flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
}; };
#define to_panel_data(p) container_of(p, struct panel_drv_data, dssdev) #define to_panel_data(p) container_of(p, struct panel_drv_data, dssdev)

5
drivers/gpu/drm/omapdrm/displays/panel-tpo-td028ttec1.c
View File

@ -53,12 +53,11 @@ static struct omap_video_timings td028ttec1_panel_timings = {
.vsync_len = 2, .vsync_len = 2,
.vback_porch = 2, .vback_porch = 2,
.vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
.hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
.data_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE, .data_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE,
.de_level = OMAPDSS_SIG_ACTIVE_HIGH, .de_level = OMAPDSS_SIG_ACTIVE_HIGH,
.sync_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE, .sync_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
.flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
}; };
#define JBT_COMMAND 0x000 #define JBT_COMMAND 0x000

4
drivers/gpu/drm/omapdrm/displays/panel-tpo-td043mtea1.c
View File

@ -86,11 +86,11 @@ static const struct omap_video_timings tpo_td043_timings = {
.vfront_porch = 39, .vfront_porch = 39,
.vback_porch = 34, .vback_porch = 34,
.vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
.hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
.data_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE, .data_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE,
.de_level = OMAPDSS_SIG_ACTIVE_HIGH, .de_level = OMAPDSS_SIG_ACTIVE_HIGH,
.sync_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE, .sync_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
.flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
}; };
#define to_panel_data(p) container_of(p, struct panel_drv_data, dssdev) #define to_panel_data(p) container_of(p, struct panel_drv_data, dssdev)

33
drivers/gpu/drm/omapdrm/dss/dispc.c
View File

@ -3157,27 +3157,15 @@ static void _dispc_mgr_set_lcd_timings(enum omap_channel channel,
dispc_write_reg(DISPC_TIMING_H(channel), timing_h); dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
dispc_write_reg(DISPC_TIMING_V(channel), timing_v); dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
switch (ovt->vsync_level) { if (ovt->flags & DISPLAY_FLAGS_VSYNC_HIGH)
case OMAPDSS_SIG_ACTIVE_LOW:
vs = true;
break;
case OMAPDSS_SIG_ACTIVE_HIGH:
vs = false; vs = false;
break; else
default: vs = true;
BUG();
}
switch (ovt->hsync_level) { if (ovt->flags & DISPLAY_FLAGS_HSYNC_HIGH)
case OMAPDSS_SIG_ACTIVE_LOW:
hs = true;
break;
case OMAPDSS_SIG_ACTIVE_HIGH:
hs = false; hs = false;
break; else
default: hs = true;
BUG();
}
switch (ovt->de_level) { switch (ovt->de_level) {
case OMAPDSS_SIG_ACTIVE_LOW: case OMAPDSS_SIG_ACTIVE_LOW:
@ -3277,8 +3265,9 @@ void dispc_mgr_set_timings(enum omap_channel channel,
t.hsync_len, t.hfront_porch, t.hback_porch, t.hsync_len, t.hfront_porch, t.hback_porch,
t.vsync_len, t.vfront_porch, t.vback_porch); t.vsync_len, t.vfront_porch, t.vback_porch);
DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n", DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n",
t.vsync_level, t.hsync_level, t.data_pclk_edge, !!(t.flags & DISPLAY_FLAGS_VSYNC_HIGH),
t.de_level, t.sync_pclk_edge); !!(t.flags & DISPLAY_FLAGS_HSYNC_HIGH),
t.data_pclk_edge, t.de_level, t.sync_pclk_edge);
DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt); DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
} else { } else {
@ -4220,12 +4209,12 @@ static const struct dispc_errata_i734_data {
.pixelclock = 16000000, .pixelclock = 16000000,
.hsync_len = 8, .hfront_porch = 4, .hback_porch = 4, .hsync_len = 8, .hfront_porch = 4, .hback_porch = 4,
.vsync_len = 1, .vfront_porch = 1, .vback_porch = 1, .vsync_len = 1, .vfront_porch = 1, .vback_porch = 1,
.vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
.hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE, .data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
.de_level = OMAPDSS_SIG_ACTIVE_HIGH, .de_level = OMAPDSS_SIG_ACTIVE_HIGH,
.sync_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE, .sync_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
.double_pixel = false, .double_pixel = false,
.flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
}, },
.ovli = { .ovli = {
.screen_width = 1, .screen_width = 1,

18
drivers/gpu/drm/omapdrm/dss/display.c
View File

@ -232,13 +232,8 @@ void videomode_to_omap_video_timings(const struct videomode *vm,
ovt->vback_porch = vm->vback_porch; ovt->vback_porch = vm->vback_porch;
ovt->vfront_porch = vm->vfront_porch; ovt->vfront_porch = vm->vfront_porch;
ovt->vsync_len = vm->vsync_len; ovt->vsync_len = vm->vsync_len;
ovt->flags = vm->flags;
ovt->vsync_level = vm->flags & DISPLAY_FLAGS_VSYNC_HIGH ?
OMAPDSS_SIG_ACTIVE_HIGH :
OMAPDSS_SIG_ACTIVE_LOW;
ovt->hsync_level = vm->flags & DISPLAY_FLAGS_HSYNC_HIGH ?
OMAPDSS_SIG_ACTIVE_HIGH :
OMAPDSS_SIG_ACTIVE_LOW;
ovt->de_level = vm->flags & DISPLAY_FLAGS_DE_HIGH ? ovt->de_level = vm->flags & DISPLAY_FLAGS_DE_HIGH ?
OMAPDSS_SIG_ACTIVE_HIGH : OMAPDSS_SIG_ACTIVE_HIGH :
OMAPDSS_SIG_ACTIVE_LOW; OMAPDSS_SIG_ACTIVE_LOW;
@ -265,16 +260,7 @@ void omap_video_timings_to_videomode(const struct omap_video_timings *ovt,
vm->vback_porch = ovt->vback_porch; vm->vback_porch = ovt->vback_porch;
vm->vfront_porch = ovt->vfront_porch; vm->vfront_porch = ovt->vfront_porch;
vm->vsync_len = ovt->vsync_len; vm->vsync_len = ovt->vsync_len;
vm->flags = ovt->flags;
if (ovt->hsync_level == OMAPDSS_SIG_ACTIVE_HIGH)
vm->flags |= DISPLAY_FLAGS_HSYNC_HIGH;
else
vm->flags |= DISPLAY_FLAGS_HSYNC_LOW;
if (ovt->vsync_level == OMAPDSS_SIG_ACTIVE_HIGH)
vm->flags |= DISPLAY_FLAGS_VSYNC_HIGH;
else
vm->flags |= DISPLAY_FLAGS_VSYNC_LOW;
if (ovt->de_level == OMAPDSS_SIG_ACTIVE_HIGH) if (ovt->de_level == OMAPDSS_SIG_ACTIVE_HIGH)
vm->flags |= DISPLAY_FLAGS_DE_HIGH; vm->flags |= DISPLAY_FLAGS_DE_HIGH;

6
drivers/gpu/drm/omapdrm/dss/dsi.c
View File

@ -4123,8 +4123,10 @@ static int dsi_display_init_dispc(struct platform_device *dsidev,
* omap_video_timings with default values * omap_video_timings with default values
*/ */
dsi->timings.flags &= ~DISPLAY_FLAGS_INTERLACED; dsi->timings.flags &= ~DISPLAY_FLAGS_INTERLACED;
dsi->timings.hsync_level = OMAPDSS_SIG_ACTIVE_HIGH; dsi->timings.flags &= ~DISPLAY_FLAGS_HSYNC_LOW;
dsi->timings.vsync_level = OMAPDSS_SIG_ACTIVE_HIGH; dsi->timings.flags |= DISPLAY_FLAGS_HSYNC_HIGH;
dsi->timings.flags &= ~DISPLAY_FLAGS_VSYNC_LOW;
dsi->timings.flags |= DISPLAY_FLAGS_VSYNC_HIGH;
dsi->timings.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE; dsi->timings.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
dsi->timings.de_level = OMAPDSS_SIG_ACTIVE_HIGH; dsi->timings.de_level = OMAPDSS_SIG_ACTIVE_HIGH;
dsi->timings.sync_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE; dsi->timings.sync_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE;

4
drivers/gpu/drm/omapdrm/dss/hdmi5_core.c
View File

@ -333,8 +333,8 @@ static void hdmi_core_video_config(struct hdmi_core_data *core,
unsigned char r = 0; unsigned char r = 0;
bool vsync_pol, hsync_pol; bool vsync_pol, hsync_pol;
vsync_pol = ovt->vsync_level == OMAPDSS_SIG_ACTIVE_HIGH; vsync_pol = !!(ovt->flags & DISPLAY_FLAGS_VSYNC_HIGH);
hsync_pol = ovt->hsync_level == OMAPDSS_SIG_ACTIVE_HIGH; hsync_pol = !!(ovt->flags & DISPLAY_FLAGS_HSYNC_HIGH);
/* Set hsync, vsync and data-enable polarity */ /* Set hsync, vsync and data-enable polarity */
r = hdmi_read_reg(base, HDMI_CORE_FC_INVIDCONF); r = hdmi_read_reg(base, HDMI_CORE_FC_INVIDCONF);

6
drivers/gpu/drm/omapdrm/dss/hdmi_wp.c
View File

@ -150,8 +150,8 @@ void hdmi_wp_video_config_interface(struct hdmi_wp_data *wp,
bool vsync_pol, hsync_pol; bool vsync_pol, hsync_pol;
DSSDBG("Enter hdmi_wp_video_config_interface\n"); DSSDBG("Enter hdmi_wp_video_config_interface\n");
vsync_pol = timings->vsync_level == OMAPDSS_SIG_ACTIVE_HIGH; vsync_pol = !!(timings->flags & DISPLAY_FLAGS_VSYNC_HIGH);
hsync_pol = timings->hsync_level == OMAPDSS_SIG_ACTIVE_HIGH; hsync_pol = !!(timings->flags & DISPLAY_FLAGS_HSYNC_HIGH);
r = hdmi_read_reg(wp->base, HDMI_WP_VIDEO_CFG); r = hdmi_read_reg(wp->base, HDMI_WP_VIDEO_CFG);
r = FLD_MOD(r, vsync_pol, 7, 7); r = FLD_MOD(r, vsync_pol, 7, 7);
@ -208,8 +208,6 @@ void hdmi_wp_init_vid_fmt_timings(struct hdmi_video_format *video_fmt,
timings->vfront_porch = param->timings.vfront_porch; timings->vfront_porch = param->timings.vfront_porch;
timings->vsync_len = param->timings.vsync_len; timings->vsync_len = param->timings.vsync_len;
timings->vsync_level = param->timings.vsync_level;
timings->hsync_level = param->timings.hsync_level;
timings->double_pixel = param->timings.double_pixel; timings->double_pixel = param->timings.double_pixel;
timings->flags = param->timings.flags; timings->flags = param->timings.flags;

4
drivers/gpu/drm/omapdrm/dss/omapdss.h
View File

@ -319,10 +319,6 @@ struct omap_video_timings {
/* Unit: line clocks */ /* Unit: line clocks */
u16 vback_porch; /* Vertical back porch */ u16 vback_porch; /* Vertical back porch */
/* Vsync logic level */
enum omap_dss_signal_level vsync_level;
/* Hsync logic level */
enum omap_dss_signal_level hsync_level;
/* Pixel clock edge to drive LCD data */ /* Pixel clock edge to drive LCD data */
enum omap_dss_signal_edge data_pclk_edge; enum omap_dss_signal_edge data_pclk_edge;
/* Data enable logic level */ /* Data enable logic level */

6
drivers/gpu/drm/omapdrm/dss/rfbi.c
View File

@ -866,8 +866,10 @@ static void rfbi_config_lcd_manager(struct omap_dss_device *dssdev)
rfbi.timings.vback_porch = 0; rfbi.timings.vback_porch = 0;
rfbi.timings.flags &= ~DISPLAY_FLAGS_INTERLACED; rfbi.timings.flags &= ~DISPLAY_FLAGS_INTERLACED;
rfbi.timings.hsync_level = OMAPDSS_SIG_ACTIVE_HIGH; rfbi.timings.flags &= ~DISPLAY_FLAGS_HSYNC_LOW;
rfbi.timings.vsync_level = OMAPDSS_SIG_ACTIVE_HIGH; rfbi.timings.flags |= DISPLAY_FLAGS_HSYNC_HIGH;
rfbi.timings.flags &= ~DISPLAY_FLAGS_VSYNC_LOW;
rfbi.timings.flags |= DISPLAY_FLAGS_VSYNC_HIGH;
rfbi.timings.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE; rfbi.timings.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
rfbi.timings.de_level = OMAPDSS_SIG_ACTIVE_HIGH; rfbi.timings.de_level = OMAPDSS_SIG_ACTIVE_HIGH;
rfbi.timings.sync_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE; rfbi.timings.sync_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE;

10
drivers/gpu/drm/omapdrm/dss/venc.c
View File

@ -273,13 +273,12 @@ const struct omap_video_timings omap_dss_pal_timings = {
.vfront_porch = 5, .vfront_porch = 5,
.vback_porch = 41, .vback_porch = 41,
.hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
.vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE, .data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
.de_level = OMAPDSS_SIG_ACTIVE_HIGH, .de_level = OMAPDSS_SIG_ACTIVE_HIGH,
.sync_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE, .sync_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE,
.flags = DISPLAY_FLAGS_INTERLACED, .flags = DISPLAY_FLAGS_INTERLACED | DISPLAY_FLAGS_HSYNC_LOW |
DISPLAY_FLAGS_VSYNC_LOW,
}; };
EXPORT_SYMBOL(omap_dss_pal_timings); EXPORT_SYMBOL(omap_dss_pal_timings);
@ -294,13 +293,12 @@ const struct omap_video_timings omap_dss_ntsc_timings = {
.vfront_porch = 6, .vfront_porch = 6,
.vback_porch = 31, .vback_porch = 31,
.hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
.vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE, .data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
.de_level = OMAPDSS_SIG_ACTIVE_HIGH, .de_level = OMAPDSS_SIG_ACTIVE_HIGH,
.sync_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE, .sync_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE,
.flags = DISPLAY_FLAGS_INTERLACED, .flags = DISPLAY_FLAGS_INTERLACED | DISPLAY_FLAGS_HSYNC_LOW |
DISPLAY_FLAGS_VSYNC_LOW,
}; };
EXPORT_SYMBOL(omap_dss_ntsc_timings); EXPORT_SYMBOL(omap_dss_ntsc_timings);

12
drivers/gpu/drm/omapdrm/omap_connector.c
View File

@ -65,12 +65,12 @@ void copy_timings_omap_to_drm(struct drm_display_mode *mode,
if (timings->double_pixel) if (timings->double_pixel)
mode->flags |= DRM_MODE_FLAG_DBLCLK; mode->flags |= DRM_MODE_FLAG_DBLCLK;
if (timings->hsync_level == OMAPDSS_SIG_ACTIVE_HIGH) if (timings->flags & DISPLAY_FLAGS_HSYNC_HIGH)
mode->flags |= DRM_MODE_FLAG_PHSYNC; mode->flags |= DRM_MODE_FLAG_PHSYNC;
else else
mode->flags |= DRM_MODE_FLAG_NHSYNC; mode->flags |= DRM_MODE_FLAG_NHSYNC;
if (timings->vsync_level == OMAPDSS_SIG_ACTIVE_HIGH) if (timings->flags & DISPLAY_FLAGS_VSYNC_HIGH)
mode->flags |= DRM_MODE_FLAG_PVSYNC; mode->flags |= DRM_MODE_FLAG_PVSYNC;
else else
mode->flags |= DRM_MODE_FLAG_NVSYNC; mode->flags |= DRM_MODE_FLAG_NVSYNC;
@ -97,14 +97,14 @@ void copy_timings_drm_to_omap(struct omap_video_timings *timings,
timings->double_pixel = !!(mode->flags & DRM_MODE_FLAG_DBLCLK); timings->double_pixel = !!(mode->flags & DRM_MODE_FLAG_DBLCLK);
if (mode->flags & DRM_MODE_FLAG_PHSYNC) if (mode->flags & DRM_MODE_FLAG_PHSYNC)
timings->hsync_level = OMAPDSS_SIG_ACTIVE_HIGH; timings->flags |= DISPLAY_FLAGS_HSYNC_HIGH;
else else
timings->hsync_level = OMAPDSS_SIG_ACTIVE_LOW; timings->flags |= DISPLAY_FLAGS_HSYNC_LOW;
if (mode->flags & DRM_MODE_FLAG_PVSYNC) if (mode->flags & DRM_MODE_FLAG_PVSYNC)
timings->vsync_level = OMAPDSS_SIG_ACTIVE_HIGH; timings->flags |= DISPLAY_FLAGS_VSYNC_HIGH;
else else
timings->vsync_level = OMAPDSS_SIG_ACTIVE_LOW; timings->flags |= DISPLAY_FLAGS_VSYNC_LOW;
timings->data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE; timings->data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
timings->de_level = OMAPDSS_SIG_ACTIVE_HIGH; timings->de_level = OMAPDSS_SIG_ACTIVE_HIGH;