net: dsa: mv88e6xxx: prefix Global 2 MGMT macros
Prefix and document the Global 2 MGMT registers macros. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -52,7 +52,7 @@ int mv88e6095_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip)
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* addresses matching 01:80:c2:00:00:2x as MGMT.
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*/
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if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_2X)) {
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err = mv88e6xxx_g2_write(chip, GLOBAL2_MGMT_EN_2X, 0xffff);
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err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_MGMT_EN_2X, 0xffff);
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if (err)
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return err;
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}
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@ -61,7 +61,8 @@ int mv88e6095_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip)
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* addresses matching 01:80:c2:00:00:0x as MGMT.
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*/
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if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_0X))
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return mv88e6xxx_g2_write(chip, GLOBAL2_MGMT_EN_0X, 0xffff);
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return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_MGMT_EN_0X,
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0xffff);
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return 0;
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}
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@ -1056,11 +1057,11 @@ int mv88e6xxx_g2_setup(struct mv88e6xxx_chip *chip)
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* highest, and send all special multicast frames to the CPU
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* port at the highest priority.
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*/
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reg = GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI | (0x7 << 4);
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reg = MV88E6XXX_G2_SWITCH_MGMT_FORCE_FLOW_CTL_PRI | (0x7 << 4);
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if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_0X) ||
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mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_2X))
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reg |= GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x7;
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err = mv88e6xxx_g2_write(chip, GLOBAL2_SWITCH_MGMT, reg);
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reg |= MV88E6XXX_G2_SWITCH_MGMT_RSVD2CPU | 0x7;
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err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_SWITCH_MGMT, reg);
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if (err)
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return err;
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@ -22,15 +22,22 @@
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#define GLOBAL2_INT_SOURCE 0x00
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#define GLOBAL2_INT_SOURCE_WATCHDOG 15
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#define GLOBAL2_INT_MASK 0x01
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#define GLOBAL2_MGMT_EN_2X 0x02
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#define GLOBAL2_MGMT_EN_0X 0x03
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/* Offset 0x02: MGMT Enable Register 2x */
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#define MV88E6XXX_G2_MGMT_EN_2X 0x02
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/* Offset 0x03: MGMT Enable Register 0x */
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#define MV88E6XXX_G2_MGMT_EN_0X 0x03
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#define GLOBAL2_FLOW_CONTROL 0x04
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#define GLOBAL2_SWITCH_MGMT 0x05
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#define GLOBAL2_SWITCH_MGMT_USE_DOUBLE_TAG_DATA BIT(15)
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#define GLOBAL2_SWITCH_MGMT_PREVENT_LOOPS BIT(14)
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#define GLOBAL2_SWITCH_MGMT_FLOW_CONTROL_MSG BIT(13)
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#define GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI BIT(7)
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#define GLOBAL2_SWITCH_MGMT_RSVD2CPU BIT(3)
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/* Offset 0x05: Switch Management Register */
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#define MV88E6XXX_G2_SWITCH_MGMT 0x05
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#define MV88E6XXX_G2_SWITCH_MGMT_USE_DOUBLE_TAG_DATA 0x8000
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#define MV88E6XXX_G2_SWITCH_MGMT_PREVENT_LOOPS 0x4000
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#define MV88E6XXX_G2_SWITCH_MGMT_FLOW_CTL_MSG 0x2000
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#define MV88E6XXX_G2_SWITCH_MGMT_FORCE_FLOW_CTL_PRI 0x0080
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#define MV88E6XXX_G2_SWITCH_MGMT_RSVD2CPU 0x0008
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/* Offset 0x06: Device Mapping Table Register */
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#define MV88E6XXX_G2_DEVICE_MAPPING 0x06
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