p71924506
/
linux_old1
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

drm: Fix warning when building docs for scdc_helper 

Fixes:
../drivers/gpu/drm/drm_scdc_helper.c:203: ERROR: Unexpected indentation.
../drivers/gpu/drm/drm_scdc_helper.c:204: WARNING: Block quote ends without a blank line; unexpected unindent.

Changes in v2:
 - Property blockquote TMDS calculations so they look pretty (Daniel)
 - Remove duplicate documentation from the header file

Signed-off-by: Sean Paul <seanpaul@chromium.org>
Reviewed-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170720200921.36897-1-seanpaul@chromium.org
This commit is contained in:
Sean Paul 2017-07-20 16:09:14 -04:00 committed by Thierry Reding
parent 8d0873a2c4
commit 6c70faf1b5
2 changed files with 19 additions and 37 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

31
drivers/gpu/drm/drm_scdc_helper.c
View File

@ -194,19 +194,26 @@ EXPORT_SYMBOL(drm_scdc_set_scrambling);
* @adapter: I2C adapter for DDC channel
* @set: ret or reset the high clock ratio
*
* TMDS clock ratio calculations go like this:
* TMDS character = 10 bit TMDS encoded value
* TMDS character rate = The rate at which TMDS characters are transmitted(Mcsc)
* TMDS bit rate = 10x TMDS character rate
* As per the spec:
* TMDS clock rate for pixel clock < 340 MHz = 1x the character rate
* = 1/10 pixel clock rate
* TMDS clock rate for pixel clock > 340 MHz = 0.25x the character rate
* = 1/40 pixel clock rate
*
* Writes to the TMDS config register over SCDC channel, and:
* sets TMDS clock ratio to 1/40 when set = 1
* sets TMDS clock ratio to 1/10 when set = 0
* TMDS clock ratio calculations go like this:
* TMDS character = 10 bit TMDS encoded value
*
* TMDS character rate = The rate at which TMDS characters are
* transmitted (Mcsc)
*
* TMDS bit rate = 10x TMDS character rate
*
* As per the spec:
* TMDS clock rate for pixel clock < 340 MHz = 1x the character
* rate = 1/10 pixel clock rate
*
* TMDS clock rate for pixel clock > 340 MHz = 0.25x the character
* rate = 1/40 pixel clock rate
*
* Writes to the TMDS config register over SCDC channel, and:
* sets TMDS clock ratio to 1/40 when set = 1
*
* sets TMDS clock ratio to 1/10 when set = 0
*
* Returns:
* True if write is successful, false otherwise.

25
include/drm/drm_scdc_helper.h
View File

@ -131,31 +131,6 @@ static inline int drm_scdc_writeb(struct i2c_adapter *adapter, u8 offset,
bool drm_scdc_get_scrambling_status(struct i2c_adapter *adapter);
/**
* drm_scdc_set_scrambling - enable scrambling
* @adapter: I2C adapter for DDC channel
* @enable: bool to indicate if scrambling is to be enabled/disabled
*
* Writes the TMDS config register over SCDC channel, and:
* enables scrambling when enable = 1
* disables scrambling when enable = 0
*
* Returns:
* True if scrambling is set/reset successfully, false otherwise.
*/
bool drm_scdc_set_scrambling(struct i2c_adapter *adapter, bool enable);
/**
* drm_scdc_set_high_tmds_clock_ratio - set TMDS clock ratio
* @adapter: I2C adapter for DDC channel
* @set: ret or reset the high clock ratio
*
* Writes to the TMDS config register over SCDC channel, and:
* sets TMDS clock ratio to 1/40 when set = 1
* sets TMDS clock ratio to 1/10 when set = 0
*
* Returns:
* True if write is successful, false otherwise.
*/
bool drm_scdc_set_high_tmds_clock_ratio(struct i2c_adapter *adapter, bool set);
#endif