ARM: dts: add sysmmu nodes for exynos5250
This patch adds System MMU nodes to all defined devices that are specific to Exynos5250 series. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Kukjin Kim <kgene@kernel.org>
This commit is contained in:
Marek Szyprowski
Kukjin Kim
parent
ecc3f340b6
commit
6cbfdd73a9
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@ -230,6 +230,7 @@ g2d@10850000 {
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interrupts = <0 91 0>;
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clocks = <&clock CLK_G2D>;
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clock-names = "fimg2d";
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iommus = <&sysmmu_g2d>;
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};
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mfc: codec@11000000 {
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@ -239,6 +240,8 @@ mfc: codec@11000000 {
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power-domains = <&pd_mfc>;
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clocks = <&clock CLK_MFC>;
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clock-names = "mfc";
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iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
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iommu-names = "left", "right";
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};
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tmu: tmu@10060000 {
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@ -693,6 +696,7 @@ gsc_0: gsc@13e00000 {
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power-domains = <&pd_gsc>;
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clocks = <&clock CLK_GSCL0>;
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clock-names = "gscl";
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iommu = <&sysmmu_gsc0>;
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};
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gsc_1: gsc@13e10000 {
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@ -702,6 +706,7 @@ gsc_1: gsc@13e10000 {
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power-domains = <&pd_gsc>;
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clocks = <&clock CLK_GSCL1>;
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clock-names = "gscl";
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iommu = <&sysmmu_gsc1>;
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};
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gsc_2: gsc@13e20000 {
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@ -711,6 +716,7 @@ gsc_2: gsc@13e20000 {
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power-domains = <&pd_gsc>;
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clocks = <&clock CLK_GSCL2>;
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clock-names = "gscl";
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iommu = <&sysmmu_gsc2>;
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};
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gsc_3: gsc@13e30000 {
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@ -720,6 +726,7 @@ gsc_3: gsc@13e30000 {
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power-domains = <&pd_gsc>;
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clocks = <&clock CLK_GSCL3>;
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clock-names = "gscl";
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iommu = <&sysmmu_gsc3>;
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};
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hdmi: hdmi {
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@ -743,6 +750,7 @@ mixer {
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clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
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<&clock CLK_SCLK_HDMI>;
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clock-names = "mixer", "hdmi", "sclk_hdmi";
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iommus = <&sysmmu_tv>;
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};
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dp_phy: video-phy@10040720 {
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@ -770,6 +778,247 @@ sss@10830000 {
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clocks = <&clock CLK_SSS>;
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clock-names = "secss";
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};
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sysmmu_g2d: sysmmu@10A60000 {
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compatible = "samsung,exynos-sysmmu";
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reg = <0x10A60000 0x1000>;
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interrupt-parent = <&combiner>;
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interrupts = <24 5>;
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clock-names = "sysmmu", "master";
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clocks = <&clock CLK_SMMU_2D>, <&clock CLK_G2D>;
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#iommu-cells = <0>;
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};
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sysmmu_mfc_r: sysmmu@11200000 {
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compatible = "samsung,exynos-sysmmu";
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reg = <0x11200000 0x1000>;
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interrupt-parent = <&combiner>;
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interrupts = <6 2>;
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power-domains = <&pd_mfc>;
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clock-names = "sysmmu", "master";
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clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
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#iommu-cells = <0>;
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};
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sysmmu_mfc_l: sysmmu@11210000 {
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compatible = "samsung,exynos-sysmmu";
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reg = <0x11210000 0x1000>;
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interrupt-parent = <&combiner>;
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interrupts = <8 5>;
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power-domains = <&pd_mfc>;
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clock-names = "sysmmu", "master";
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clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
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#iommu-cells = <0>;
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};
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sysmmu_rotator: sysmmu@11D40000 {
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compatible = "samsung,exynos-sysmmu";
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reg = <0x11D40000 0x1000>;
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interrupt-parent = <&combiner>;
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interrupts = <4 0>;
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clock-names = "sysmmu", "master";
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clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
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#iommu-cells = <0>;
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};
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sysmmu_jpeg: sysmmu@11F20000 {
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compatible = "samsung,exynos-sysmmu";
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reg = <0x11F20000 0x1000>;
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interrupt-parent = <&combiner>;
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interrupts = <4 2>;
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power-domains = <&pd_gsc>;
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clock-names = "sysmmu", "master";
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clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
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#iommu-cells = <0>;
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};
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sysmmu_fimc_isp: sysmmu@13260000 {
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compatible = "samsung,exynos-sysmmu";
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reg = <0x13260000 0x1000>;
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interrupt-parent = <&combiner>;
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interrupts = <10 6>;
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clock-names = "sysmmu";
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clocks = <&clock CLK_SMMU_FIMC_ISP>;
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#iommu-cells = <0>;
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};
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sysmmu_fimc_drc: sysmmu@13270000 {
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compatible = "samsung,exynos-sysmmu";
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reg = <0x13270000 0x1000>;
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interrupt-parent = <&combiner>;
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interrupts = <11 6>;
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clock-names = "sysmmu";
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clocks = <&clock CLK_SMMU_FIMC_DRC>;
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#iommu-cells = <0>;
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};
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sysmmu_fimc_fd: sysmmu@132A0000 {
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compatible = "samsung,exynos-sysmmu";
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reg = <0x132A0000 0x1000>;
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interrupt-parent = <&combiner>;
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interrupts = <5 0>;
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clock-names = "sysmmu";
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clocks = <&clock CLK_SMMU_FIMC_FD>;
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#iommu-cells = <0>;
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};
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sysmmu_fimc_scc: sysmmu@13280000 {
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compatible = "samsung,exynos-sysmmu";
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reg = <0x13280000 0x1000>;
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interrupt-parent = <&combiner>;
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interrupts = <5 2>;
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clock-names = "sysmmu";
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clocks = <&clock CLK_SMMU_FIMC_SCC>;
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#iommu-cells = <0>;
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};
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sysmmu_fimc_scp: sysmmu@13290000 {
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compatible = "samsung,exynos-sysmmu";
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reg = <0x13290000 0x1000>;
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interrupt-parent = <&combiner>;
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interrupts = <3 6>;
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clock-names = "sysmmu";
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clocks = <&clock CLK_SMMU_FIMC_SCP>;
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#iommu-cells = <0>;
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};
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sysmmu_fimc_mcuctl: sysmmu@132B0000 {
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compatible = "samsung,exynos-sysmmu";
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reg = <0x132B0000 0x1000>;
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interrupt-parent = <&combiner>;
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interrupts = <5 4>;
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clock-names = "sysmmu";
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clocks = <&clock CLK_SMMU_FIMC_MCU>;
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#iommu-cells = <0>;
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};
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sysmmu_fimc_odc: sysmmu@132C0000 {
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compatible = "samsung,exynos-sysmmu";
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reg = <0x132C0000 0x1000>;
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interrupt-parent = <&combiner>;
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interrupts = <11 0>;
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clock-names = "sysmmu";
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clocks = <&clock CLK_SMMU_FIMC_ODC>;
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#iommu-cells = <0>;
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};
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sysmmu_fimc_dis0: sysmmu@132D0000 {
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compatible = "samsung,exynos-sysmmu";
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reg = <0x132D0000 0x1000>;
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interrupt-parent = <&combiner>;
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interrupts = <10 4>;
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clock-names = "sysmmu";
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clocks = <&clock CLK_SMMU_FIMC_DIS0>;
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#iommu-cells = <0>;
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};
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sysmmu_fimc_dis1: sysmmu@132E0000{
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compatible = "samsung,exynos-sysmmu";
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reg = <0x132E0000 0x1000>;
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interrupt-parent = <&combiner>;
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interrupts = <9 4>;
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clock-names = "sysmmu";
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clocks = <&clock CLK_SMMU_FIMC_DIS1>;
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#iommu-cells = <0>;
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};
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sysmmu_fimc_3dnr: sysmmu@132F0000 {
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compatible = "samsung,exynos-sysmmu";
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reg = <0x132F0000 0x1000>;
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interrupt-parent = <&combiner>;
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interrupts = <5 6>;
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clock-names = "sysmmu";
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clocks = <&clock CLK_SMMU_FIMC_3DNR>;
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#iommu-cells = <0>;
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};
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sysmmu_fimc_lite0: sysmmu@13C40000 {
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compatible = "samsung,exynos-sysmmu";
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reg = <0x13C40000 0x1000>;
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interrupt-parent = <&combiner>;
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interrupts = <3 4>;
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power-domains = <&pd_gsc>;
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clock-names = "sysmmu", "master";
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clocks = <&clock CLK_SMMU_FIMC_LITE0>, <&clock CLK_CAMIF_TOP>;
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#iommu-cells = <0>;
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};
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sysmmu_fimc_lite1: sysmmu@13C50000 {
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compatible = "samsung,exynos-sysmmu";
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reg = <0x13C50000 0x1000>;
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interrupt-parent = <&combiner>;
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interrupts = <24 1>;
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power-domains = <&pd_gsc>;
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clock-names = "sysmmu", "master";
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clocks = <&clock CLK_SMMU_FIMC_LITE1>, <&clock CLK_CAMIF_TOP>;
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#iommu-cells = <0>;
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};
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sysmmu_gsc0: sysmmu@13E80000 {
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compatible = "samsung,exynos-sysmmu";
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reg = <0x13E80000 0x1000>;
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interrupt-parent = <&combiner>;
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interrupts = <2 0>;
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power-domains = <&pd_gsc>;
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clock-names = "sysmmu", "master";
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clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
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#iommu-cells = <0>;
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};
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sysmmu_gsc1: sysmmu@13E90000 {
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compatible = "samsung,exynos-sysmmu";
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reg = <0x13E90000 0x1000>;
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interrupt-parent = <&combiner>;
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interrupts = <2 2>;
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power-domains = <&pd_gsc>;
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clock-names = "sysmmu", "master";
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clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
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#iommu-cells = <0>;
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};
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sysmmu_gsc2: sysmmu@13EA0000 {
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compatible = "samsung,exynos-sysmmu";
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reg = <0x13EA0000 0x1000>;
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interrupt-parent = <&combiner>;
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interrupts = <2 4>;
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power-domains = <&pd_gsc>;
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clock-names = "sysmmu", "master";
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clocks = <&clock CLK_SMMU_GSCL2>, <&clock CLK_GSCL2>;
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#iommu-cells = <0>;
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};
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sysmmu_gsc3: sysmmu@13EB0000 {
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compatible = "samsung,exynos-sysmmu";
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reg = <0x13EB0000 0x1000>;
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interrupt-parent = <&combiner>;
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interrupts = <2 6>;
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power-domains = <&pd_gsc>;
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clock-names = "sysmmu", "master";
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clocks = <&clock CLK_SMMU_GSCL3>, <&clock CLK_GSCL3>;
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#iommu-cells = <0>;
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};
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sysmmu_fimd1: sysmmu@14640000 {
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compatible = "samsung,exynos-sysmmu";
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reg = <0x14640000 0x1000>;
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interrupt-parent = <&combiner>;
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interrupts = <3 2>;
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power-domains = <&pd_disp1>;
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clock-names = "sysmmu", "master";
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clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
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#iommu-cells = <0>;
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};
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sysmmu_tv: sysmmu@14650000 {
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compatible = "samsung,exynos-sysmmu";
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reg = <0x14650000 0x1000>;
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interrupt-parent = <&combiner>;
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interrupts = <7 4>;
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power-domains = <&pd_disp1>;
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clock-names = "sysmmu", "master";
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clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>;
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#iommu-cells = <0>;
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};
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};
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&dp {
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@ -784,6 +1033,7 @@ &fimd {
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power-domains = <&pd_disp1>;
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clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
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clock-names = "sclk_fimd", "fimd";
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iommus = <&sysmmu_fimd1>;
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};
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&rtc {
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