misc: xilinx_sdfec: Store driver config and state
Stores configuration based on parameters from the DT node and values from the SD-FEC core plus reads the default state from the SD-FEC core. To obtain values from the core register read, write capabilities have been added plus related register map details. Tested-by: Dragan Cvetic <dragan.cvetic@xilinx.com> Signed-off-by: Derek Kiernan <derek.kiernan@xilinx.com> Signed-off-by: Dragan Cvetic <dragan.cvetic@xilinx.com> Link: https://lore.kernel.org/r/1564216438-322406-2-git-send-email-dragan.cvetic@xilinx.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Dragan Cvetic
Greg Kroah-Hartman
parent
77e38c19f3
commit
6d54e45568
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@ -20,11 +20,92 @@
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#include <linux/slab.h>
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#include <linux/clk.h>
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#include <uapi/misc/xilinx_sdfec.h>
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#define DEV_NAME_LEN 12
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static struct idr dev_idr;
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static struct mutex dev_idr_lock;
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/* Xilinx SDFEC Register Map */
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/* CODE_WRI_PROTECT Register */
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#define XSDFEC_CODE_WR_PROTECT_ADDR (0x4)
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/* ACTIVE Register */
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#define XSDFEC_ACTIVE_ADDR (0x8)
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#define XSDFEC_IS_ACTIVITY_SET (0x1)
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/* AXIS_WIDTH Register */
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#define XSDFEC_AXIS_WIDTH_ADDR (0xC)
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#define XSDFEC_AXIS_DOUT_WORDS_LSB (5)
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#define XSDFEC_AXIS_DOUT_WIDTH_LSB (3)
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#define XSDFEC_AXIS_DIN_WORDS_LSB (2)
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#define XSDFEC_AXIS_DIN_WIDTH_LSB (0)
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/* AXIS_ENABLE Register */
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#define XSDFEC_AXIS_ENABLE_ADDR (0x10)
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#define XSDFEC_AXIS_OUT_ENABLE_MASK (0x38)
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#define XSDFEC_AXIS_IN_ENABLE_MASK (0x7)
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#define XSDFEC_AXIS_ENABLE_MASK \
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(XSDFEC_AXIS_OUT_ENABLE_MASK | XSDFEC_AXIS_IN_ENABLE_MASK)
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/* FEC_CODE Register */
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#define XSDFEC_FEC_CODE_ADDR (0x14)
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/* ORDER Register Map */
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#define XSDFEC_ORDER_ADDR (0x18)
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/* Interrupt Status Register */
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#define XSDFEC_ISR_ADDR (0x1C)
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/* Interrupt Status Register Bit Mask */
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#define XSDFEC_ISR_MASK (0x3F)
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/* Write Only - Interrupt Enable Register */
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#define XSDFEC_IER_ADDR (0x20)
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/* Write Only - Interrupt Disable Register */
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#define XSDFEC_IDR_ADDR (0x24)
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/* Read Only - Interrupt Mask Register */
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#define XSDFEC_IMR_ADDR (0x28)
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/* ECC Interrupt Status Register */
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#define XSDFEC_ECC_ISR_ADDR (0x2C)
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/* Single Bit Errors */
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#define XSDFEC_ECC_ISR_SBE_MASK (0x7FF)
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/* PL Initialize Single Bit Errors */
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#define XSDFEC_PL_INIT_ECC_ISR_SBE_MASK (0x3C00000)
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/* Multi Bit Errors */
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#define XSDFEC_ECC_ISR_MBE_MASK (0x3FF800)
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/* PL Initialize Multi Bit Errors */
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#define XSDFEC_PL_INIT_ECC_ISR_MBE_MASK (0x3C000000)
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/* Multi Bit Error to Event Shift */
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#define XSDFEC_ECC_ISR_MBE_TO_EVENT_SHIFT (11)
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/* PL Initialize Multi Bit Error to Event Shift */
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#define XSDFEC_PL_INIT_ECC_ISR_MBE_TO_EVENT_SHIFT (4)
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/* ECC Interrupt Status Bit Mask */
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#define XSDFEC_ECC_ISR_MASK (XSDFEC_ECC_ISR_SBE_MASK | XSDFEC_ECC_ISR_MBE_MASK)
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/* ECC Interrupt Status PL Initialize Bit Mask */
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#define XSDFEC_PL_INIT_ECC_ISR_MASK \
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(XSDFEC_PL_INIT_ECC_ISR_SBE_MASK | XSDFEC_PL_INIT_ECC_ISR_MBE_MASK)
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/* ECC Interrupt Status All Bit Mask */
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#define XSDFEC_ALL_ECC_ISR_MASK \
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(XSDFEC_ECC_ISR_MASK | XSDFEC_PL_INIT_ECC_ISR_MASK)
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/* ECC Interrupt Status Single Bit Errors Mask */
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#define XSDFEC_ALL_ECC_ISR_SBE_MASK \
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(XSDFEC_ECC_ISR_SBE_MASK | XSDFEC_PL_INIT_ECC_ISR_SBE_MASK)
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/* ECC Interrupt Status Multi Bit Errors Mask */
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#define XSDFEC_ALL_ECC_ISR_MBE_MASK \
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(XSDFEC_ECC_ISR_MBE_MASK | XSDFEC_PL_INIT_ECC_ISR_MBE_MASK)
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/* Write Only - ECC Interrupt Enable Register */
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#define XSDFEC_ECC_IER_ADDR (0x30)
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/* Write Only - ECC Interrupt Disable Register */
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#define XSDFEC_ECC_IDR_ADDR (0x34)
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/* Read Only - ECC Interrupt Mask Register */
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#define XSDFEC_ECC_IMR_ADDR (0x38)
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/* BYPASS Register */
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#define XSDFEC_BYPASS_ADDR (0x3C)
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/**
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* struct xsdfec_clks - For managing SD-FEC clocks
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* @core_clk: Main processing clock for core
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@ -49,31 +130,237 @@ struct xsdfec_clks {
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/**
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* struct xsdfec_dev - Driver data for SDFEC
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* @miscdev: Misc device handle
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* @clks: Clocks managed by the SDFEC driver
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* @regs: device physical base address
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* @dev: pointer to device struct
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* @miscdev: Misc device handle
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* @error_data_lock: Error counter and states spinlock
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* @clks: Clocks managed by the SDFEC driver
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* @config: Configuration of the SDFEC device
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* @dev_name: Device name
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* @state: State of the SDFEC device
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* @error_data_lock: Error counter and states spinlock
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* @dev_id: Device ID
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*
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* This structure contains necessary state for SDFEC driver to operate
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*/
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struct xsdfec_dev {
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struct miscdevice miscdev;
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struct xsdfec_clks clks;
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void __iomem *regs;
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struct device *dev;
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struct miscdevice miscdev;
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struct xsdfec_config config;
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char dev_name[DEV_NAME_LEN];
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enum xsdfec_state state;
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/* Spinlock to protect state_updated and stats_updated */
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spinlock_t error_data_lock;
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struct xsdfec_clks clks;
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char dev_name[DEV_NAME_LEN];
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int dev_id;
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};
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static inline void xsdfec_regwrite(struct xsdfec_dev *xsdfec, u32 addr,
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u32 value)
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{
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dev_dbg(xsdfec->dev, "Writing 0x%x to offset 0x%x", value, addr);
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iowrite32(value, xsdfec->regs + addr);
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}
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static inline u32 xsdfec_regread(struct xsdfec_dev *xsdfec, u32 addr)
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{
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u32 rval;
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rval = ioread32(xsdfec->regs + addr);
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dev_dbg(xsdfec->dev, "Read value = 0x%x from offset 0x%x", rval, addr);
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return rval;
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}
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static void update_bool_config_from_reg(struct xsdfec_dev *xsdfec,
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u32 reg_offset, u32 bit_num,
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char *config_value)
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{
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u32 reg_val;
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u32 bit_mask = 1 << bit_num;
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reg_val = xsdfec_regread(xsdfec, reg_offset);
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*config_value = (reg_val & bit_mask) > 0;
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}
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static void update_config_from_hw(struct xsdfec_dev *xsdfec)
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{
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u32 reg_value;
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bool sdfec_started;
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/* Update the Order */
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reg_value = xsdfec_regread(xsdfec, XSDFEC_ORDER_ADDR);
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xsdfec->config.order = reg_value;
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update_bool_config_from_reg(xsdfec, XSDFEC_BYPASS_ADDR,
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0, /* Bit Number, maybe change to mask */
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&xsdfec->config.bypass);
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update_bool_config_from_reg(xsdfec, XSDFEC_CODE_WR_PROTECT_ADDR,
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0, /* Bit Number */
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&xsdfec->config.code_wr_protect);
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reg_value = xsdfec_regread(xsdfec, XSDFEC_IMR_ADDR);
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xsdfec->config.irq.enable_isr = (reg_value & XSDFEC_ISR_MASK) > 0;
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reg_value = xsdfec_regread(xsdfec, XSDFEC_ECC_IMR_ADDR);
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xsdfec->config.irq.enable_ecc_isr =
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(reg_value & XSDFEC_ECC_ISR_MASK) > 0;
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reg_value = xsdfec_regread(xsdfec, XSDFEC_AXIS_ENABLE_ADDR);
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sdfec_started = (reg_value & XSDFEC_AXIS_IN_ENABLE_MASK) > 0;
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if (sdfec_started)
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xsdfec->state = XSDFEC_STARTED;
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else
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xsdfec->state = XSDFEC_STOPPED;
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}
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static u32
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xsdfec_translate_axis_width_cfg_val(enum xsdfec_axis_width axis_width_cfg)
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{
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u32 axis_width_field = 0;
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switch (axis_width_cfg) {
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case XSDFEC_1x128b:
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axis_width_field = 0;
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break;
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case XSDFEC_2x128b:
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axis_width_field = 1;
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break;
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case XSDFEC_4x128b:
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axis_width_field = 2;
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break;
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}
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return axis_width_field;
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}
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static u32 xsdfec_translate_axis_words_cfg_val(enum xsdfec_axis_word_include
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axis_word_inc_cfg)
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{
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u32 axis_words_field = 0;
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if (axis_word_inc_cfg == XSDFEC_FIXED_VALUE ||
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axis_word_inc_cfg == XSDFEC_IN_BLOCK)
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axis_words_field = 0;
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else if (axis_word_inc_cfg == XSDFEC_PER_AXI_TRANSACTION)
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axis_words_field = 1;
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return axis_words_field;
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}
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static int xsdfec_cfg_axi_streams(struct xsdfec_dev *xsdfec)
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{
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u32 reg_value;
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u32 dout_words_field;
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u32 dout_width_field;
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u32 din_words_field;
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u32 din_width_field;
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struct xsdfec_config *config = &xsdfec->config;
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/* translate config info to register values */
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dout_words_field =
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xsdfec_translate_axis_words_cfg_val(config->dout_word_include);
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dout_width_field =
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xsdfec_translate_axis_width_cfg_val(config->dout_width);
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din_words_field =
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xsdfec_translate_axis_words_cfg_val(config->din_word_include);
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din_width_field =
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xsdfec_translate_axis_width_cfg_val(config->din_width);
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reg_value = dout_words_field << XSDFEC_AXIS_DOUT_WORDS_LSB;
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reg_value |= dout_width_field << XSDFEC_AXIS_DOUT_WIDTH_LSB;
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reg_value |= din_words_field << XSDFEC_AXIS_DIN_WORDS_LSB;
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reg_value |= din_width_field << XSDFEC_AXIS_DIN_WIDTH_LSB;
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xsdfec_regwrite(xsdfec, XSDFEC_AXIS_WIDTH_ADDR, reg_value);
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return 0;
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}
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static const struct file_operations xsdfec_fops = {
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.owner = THIS_MODULE,
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};
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static int xsdfec_parse_of(struct xsdfec_dev *xsdfec)
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{
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struct device *dev = xsdfec->dev;
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struct device_node *node = dev->of_node;
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int rval;
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const char *fec_code;
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u32 din_width;
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u32 din_word_include;
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u32 dout_width;
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u32 dout_word_include;
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rval = of_property_read_string(node, "xlnx,sdfec-code", &fec_code);
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if (rval < 0)
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return rval;
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if (!strcasecmp(fec_code, "ldpc"))
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xsdfec->config.code = XSDFEC_LDPC_CODE;
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else if (!strcasecmp(fec_code, "turbo"))
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xsdfec->config.code = XSDFEC_TURBO_CODE;
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else
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return -EINVAL;
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rval = of_property_read_u32(node, "xlnx,sdfec-din-words",
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&din_word_include);
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if (rval < 0)
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return rval;
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if (din_word_include < XSDFEC_AXIS_WORDS_INCLUDE_MAX)
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xsdfec->config.din_word_include = din_word_include;
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else
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return -EINVAL;
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rval = of_property_read_u32(node, "xlnx,sdfec-din-width", &din_width);
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if (rval < 0)
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return rval;
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switch (din_width) {
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/* Fall through and set for valid values */
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case XSDFEC_1x128b:
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case XSDFEC_2x128b:
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case XSDFEC_4x128b:
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xsdfec->config.din_width = din_width;
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break;
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default:
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return -EINVAL;
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}
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rval = of_property_read_u32(node, "xlnx,sdfec-dout-words",
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&dout_word_include);
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if (rval < 0)
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return rval;
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if (dout_word_include < XSDFEC_AXIS_WORDS_INCLUDE_MAX)
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xsdfec->config.dout_word_include = dout_word_include;
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else
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return -EINVAL;
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rval = of_property_read_u32(node, "xlnx,sdfec-dout-width", &dout_width);
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if (rval < 0)
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return rval;
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switch (dout_width) {
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/* Fall through and set for valid values */
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case XSDFEC_1x128b:
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case XSDFEC_2x128b:
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case XSDFEC_4x128b:
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xsdfec->config.dout_width = dout_width;
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break;
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default:
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return -EINVAL;
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}
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/* Write LDPC to CODE Register */
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xsdfec_regwrite(xsdfec, XSDFEC_FEC_CODE_ADDR, xsdfec->config.code);
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xsdfec_cfg_axi_streams(xsdfec);
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return 0;
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}
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static int xsdfec_clk_init(struct platform_device *pdev,
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struct xsdfec_clks *clks)
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{
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@ -260,6 +547,12 @@ static int xsdfec_probe(struct platform_device *pdev)
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goto err_xsdfec_dev;
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}
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err = xsdfec_parse_of(xsdfec);
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if (err < 0)
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goto err_xsdfec_dev;
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update_config_from_hw(xsdfec);
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/* Save driver private data */
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platform_set_drvdata(pdev, xsdfec);
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@ -0,0 +1,138 @@
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/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
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/*
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* Xilinx SD-FEC
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*
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* Copyright (C) 2019 Xilinx, Inc.
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*
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* Description:
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* This driver is developed for SDFEC16 IP. It provides a char device
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* in sysfs and supports file operations like open(), close() and ioctl().
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*/
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#ifndef __XILINX_SDFEC_H__
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#define __XILINX_SDFEC_H__
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#include <linux/types.h>
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/**
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* enum xsdfec_code - Code Type.
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* @XSDFEC_TURBO_CODE: Driver is configured for Turbo mode.
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* @XSDFEC_LDPC_CODE: Driver is configured for LDPC mode.
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*
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* This enum is used to indicate the mode of the driver. The mode is determined
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* by checking which codes are set in the driver. Note that the mode cannot be
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* changed by the driver.
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*/
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enum xsdfec_code {
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XSDFEC_TURBO_CODE = 0,
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XSDFEC_LDPC_CODE,
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};
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/**
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* enum xsdfec_order - Order
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* @XSDFEC_MAINTAIN_ORDER: Maintain order execution of blocks.
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* @XSDFEC_OUT_OF_ORDER: Out-of-order execution of blocks.
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*
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* This enum is used to indicate whether the order of blocks can change from
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* input to output.
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*/
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enum xsdfec_order {
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XSDFEC_MAINTAIN_ORDER = 0,
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XSDFEC_OUT_OF_ORDER,
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};
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/**
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* enum xsdfec_state - State.
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* @XSDFEC_INIT: Driver is initialized.
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* @XSDFEC_STARTED: Driver is started.
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* @XSDFEC_STOPPED: Driver is stopped.
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* @XSDFEC_NEEDS_RESET: Driver needs to be reset.
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* @XSDFEC_PL_RECONFIGURE: Programmable Logic needs to be recofigured.
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*
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* This enum is used to indicate the state of the driver.
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*/
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enum xsdfec_state {
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XSDFEC_INIT = 0,
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XSDFEC_STARTED,
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XSDFEC_STOPPED,
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XSDFEC_NEEDS_RESET,
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XSDFEC_PL_RECONFIGURE,
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};
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/**
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* enum xsdfec_axis_width - AXIS_WIDTH.DIN Setting for 128-bit width.
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* @XSDFEC_1x128b: DIN data input stream consists of a 128-bit lane
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* @XSDFEC_2x128b: DIN data input stream consists of two 128-bit lanes
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* @XSDFEC_4x128b: DIN data input stream consists of four 128-bit lanes
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*
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* This enum is used to indicate the AXIS_WIDTH.DIN setting for 128-bit width.
|
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* The number of lanes of the DIN data input stream depends upon the
|
||||
* AXIS_WIDTH.DIN parameter.
|
||||
*/
|
||||
enum xsdfec_axis_width {
|
||||
XSDFEC_1x128b = 1,
|
||||
XSDFEC_2x128b = 2,
|
||||
XSDFEC_4x128b = 4,
|
||||
};
|
||||
|
||||
/**
|
||||
* enum xsdfec_axis_word_include - Words Configuration.
|
||||
* @XSDFEC_FIXED_VALUE: Fixed, the DIN_WORDS AXI4-Stream interface is removed
|
||||
* from the IP instance and is driven with the specified
|
||||
* number of words.
|
||||
* @XSDFEC_IN_BLOCK: In Block, configures the IP instance to expect a single
|
||||
* DIN_WORDS value per input code block. The DIN_WORDS
|
||||
* interface is present.
|
||||
* @XSDFEC_PER_AXI_TRANSACTION: Per Transaction, configures the IP instance to
|
||||
* expect one DIN_WORDS value per input transaction on the DIN interface. The
|
||||
* DIN_WORDS interface is present.
|
||||
* @XSDFEC_AXIS_WORDS_INCLUDE_MAX: Used to indicate out of bound Words
|
||||
* Configurations.
|
||||
*
|
||||
* This enum is used to specify the DIN_WORDS configuration.
|
||||
*/
|
||||
enum xsdfec_axis_word_include {
|
||||
XSDFEC_FIXED_VALUE = 0,
|
||||
XSDFEC_IN_BLOCK,
|
||||
XSDFEC_PER_AXI_TRANSACTION,
|
||||
XSDFEC_AXIS_WORDS_INCLUDE_MAX,
|
||||
};
|
||||
|
||||
/**
|
||||
* struct xsdfec_irq - Enabling or Disabling Interrupts.
|
||||
* @enable_isr: If true enables the ISR
|
||||
* @enable_ecc_isr: If true enables the ECC ISR
|
||||
*/
|
||||
struct xsdfec_irq {
|
||||
__s8 enable_isr;
|
||||
__s8 enable_ecc_isr;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct xsdfec_config - Configuration of SD-FEC core.
|
||||
* @code: The codes being used by the SD-FEC instance
|
||||
* @order: Order of Operation
|
||||
* @din_width: Width of the DIN AXI4-Stream
|
||||
* @din_word_include: How DIN_WORDS are inputted
|
||||
* @dout_width: Width of the DOUT AXI4-Stream
|
||||
* @dout_word_include: HOW DOUT_WORDS are outputted
|
||||
* @irq: Enabling or disabling interrupts
|
||||
* @bypass: Is the core being bypassed
|
||||
* @code_wr_protect: Is write protection of LDPC codes enabled
|
||||
*/
|
||||
struct xsdfec_config {
|
||||
__u32 code;
|
||||
__u32 order;
|
||||
__u32 din_width;
|
||||
__u32 din_word_include;
|
||||
__u32 dout_width;
|
||||
__u32 dout_word_include;
|
||||
struct xsdfec_irq irq;
|
||||
__s8 bypass;
|
||||
__s8 code_wr_protect;
|
||||
};
|
||||
|
||||
/*
|
||||
* XSDFEC IOCTL List
|
||||
*/
|
||||
#define XSDFEC_MAGIC 'f'
|
||||
#endif /* __XILINX_SDFEC_H__ */
|
||||
Loading…
Reference in New Issue