iio: adc: mxs-lradc: Add support for ADC driver
Add support for sixteen-channel 12-bit resolution ADC and its functions, which include general-purpose ADC readings, battery voltage measurement, and die temperature measurement. Signed-off-by: Ksenija Stanojevic <ksenija.stanojevic@gmail.com> Reviewed-by: Jonathan Cameron <jic23@kernel.org> Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Lee Jones <lee.jones@linaro.org>
This commit is contained in:
Ksenija Stanojevic
Lee Jones
parent
ead25133e9
commit
6dd112b9f8
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@ -229,6 +229,19 @@ config EXYNOS_ADC
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To compile this driver as a module, choose M here: the module will be
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called exynos_adc.
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config MXS_LRADC_ADC
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tristate "Freescale i.MX23/i.MX28 LRADC ADC"
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depends on MFD_MXS_LRADC
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select IIO_BUFFER
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select IIO_TRIGGERED_BUFFER
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help
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Say yes here to build support for the ADC functions of the
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i.MX23/i.MX28 LRADC. This includes general-purpose ADC readings,
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battery voltage measurement, and die temperature measurement.
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This driver can also be built as a module. If so, the module will be
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called mxs-lradc-adc.
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config FSL_MX25_ADC
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tristate "Freescale MX25 ADC driver"
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depends on MFD_MX25_TSADC
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@ -39,6 +39,7 @@ obj-$(CONFIG_MCP3422) += mcp3422.o
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obj-$(CONFIG_MEDIATEK_MT6577_AUXADC) += mt6577_auxadc.o
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obj-$(CONFIG_MEN_Z188_ADC) += men_z188_adc.o
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obj-$(CONFIG_MESON_SARADC) += meson_saradc.o
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obj-$(CONFIG_MXS_LRADC_ADC) += mxs-lradc-adc.o
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obj-$(CONFIG_MXS_LRADC) += mxs-lradc.o
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obj-$(CONFIG_NAU7802) += nau7802.o
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obj-$(CONFIG_PALMAS_GPADC) += palmas_gpadc.o
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@ -0,0 +1,843 @@
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/*
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* Freescale MXS LRADC ADC driver
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*
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* Copyright (c) 2012 DENX Software Engineering, GmbH.
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* Copyright (c) 2017 Ksenija Stanojevic <ksenija.stanojevic@gmail.com>
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*
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* Authors:
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* Marek Vasut <marex@denx.de>
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* Ksenija Stanojevic <ksenija.stanojevic@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/completion.h>
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/mfd/core.h>
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#include <linux/mfd/mxs-lradc.h>
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#include <linux/module.h>
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#include <linux/of_irq.h>
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#include <linux/platform_device.h>
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#include <linux/sysfs.h>
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#include <linux/iio/buffer.h>
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#include <linux/iio/iio.h>
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#include <linux/iio/trigger.h>
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#include <linux/iio/trigger_consumer.h>
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#include <linux/iio/triggered_buffer.h>
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#include <linux/iio/sysfs.h>
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/*
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* Make this runtime configurable if necessary. Currently, if the buffered mode
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* is enabled, the LRADC takes LRADC_DELAY_TIMER_LOOP samples of data before
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* triggering IRQ. The sampling happens every (LRADC_DELAY_TIMER_PER / 2000)
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* seconds. The result is that the samples arrive every 500mS.
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*/
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#define LRADC_DELAY_TIMER_PER 200
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#define LRADC_DELAY_TIMER_LOOP 5
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#define VREF_MV_BASE 1850
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const char *mx23_lradc_adc_irq_names[] = {
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"mxs-lradc-channel0",
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"mxs-lradc-channel1",
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"mxs-lradc-channel2",
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"mxs-lradc-channel3",
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"mxs-lradc-channel4",
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"mxs-lradc-channel5",
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};
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const char *mx28_lradc_adc_irq_names[] = {
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"mxs-lradc-thresh0",
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"mxs-lradc-thresh1",
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"mxs-lradc-channel0",
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"mxs-lradc-channel1",
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"mxs-lradc-channel2",
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"mxs-lradc-channel3",
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"mxs-lradc-channel4",
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"mxs-lradc-channel5",
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"mxs-lradc-button0",
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"mxs-lradc-button1",
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};
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static const u32 mxs_lradc_adc_vref_mv[][LRADC_MAX_TOTAL_CHANS] = {
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[IMX23_LRADC] = {
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VREF_MV_BASE, /* CH0 */
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VREF_MV_BASE, /* CH1 */
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VREF_MV_BASE, /* CH2 */
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VREF_MV_BASE, /* CH3 */
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VREF_MV_BASE, /* CH4 */
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VREF_MV_BASE, /* CH5 */
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VREF_MV_BASE * 2, /* CH6 VDDIO */
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VREF_MV_BASE * 4, /* CH7 VBATT */
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VREF_MV_BASE, /* CH8 Temp sense 0 */
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VREF_MV_BASE, /* CH9 Temp sense 1 */
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VREF_MV_BASE, /* CH10 */
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VREF_MV_BASE, /* CH11 */
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VREF_MV_BASE, /* CH12 USB_DP */
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VREF_MV_BASE, /* CH13 USB_DN */
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VREF_MV_BASE, /* CH14 VBG */
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VREF_MV_BASE * 4, /* CH15 VDD5V */
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},
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[IMX28_LRADC] = {
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VREF_MV_BASE, /* CH0 */
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VREF_MV_BASE, /* CH1 */
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VREF_MV_BASE, /* CH2 */
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VREF_MV_BASE, /* CH3 */
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VREF_MV_BASE, /* CH4 */
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VREF_MV_BASE, /* CH5 */
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VREF_MV_BASE, /* CH6 */
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VREF_MV_BASE * 4, /* CH7 VBATT */
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VREF_MV_BASE, /* CH8 Temp sense 0 */
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VREF_MV_BASE, /* CH9 Temp sense 1 */
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VREF_MV_BASE * 2, /* CH10 VDDIO */
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VREF_MV_BASE, /* CH11 VTH */
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VREF_MV_BASE * 2, /* CH12 VDDA */
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VREF_MV_BASE, /* CH13 VDDD */
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VREF_MV_BASE, /* CH14 VBG */
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VREF_MV_BASE * 4, /* CH15 VDD5V */
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},
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};
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enum mxs_lradc_divbytwo {
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MXS_LRADC_DIV_DISABLED = 0,
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MXS_LRADC_DIV_ENABLED,
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};
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struct mxs_lradc_scale {
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unsigned int integer;
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unsigned int nano;
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};
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struct mxs_lradc_adc {
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struct mxs_lradc *lradc;
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struct device *dev;
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void __iomem *base;
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u32 buffer[10];
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struct iio_trigger *trig;
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struct completion completion;
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spinlock_t lock;
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const u32 *vref_mv;
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struct mxs_lradc_scale scale_avail[LRADC_MAX_TOTAL_CHANS][2];
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unsigned long is_divided;
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};
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/* Raw I/O operations */
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static int mxs_lradc_adc_read_single(struct iio_dev *iio_dev, int chan,
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int *val)
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{
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struct mxs_lradc_adc *adc = iio_priv(iio_dev);
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struct mxs_lradc *lradc = adc->lradc;
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int ret;
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/*
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* See if there is no buffered operation in progress. If there is simply
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* bail out. This can be improved to support both buffered and raw IO at
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* the same time, yet the code becomes horribly complicated. Therefore I
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* applied KISS principle here.
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*/
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ret = iio_device_claim_direct_mode(iio_dev);
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if (ret)
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return ret;
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reinit_completion(&adc->completion);
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/*
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* No buffered operation in progress, map the channel and trigger it.
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* Virtual channel 0 is always used here as the others are always not
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* used if doing raw sampling.
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*/
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if (lradc->soc == IMX28_LRADC)
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writel(LRADC_CTRL1_LRADC_IRQ_EN(0),
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adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
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writel(0x1, adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);
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/* Enable / disable the divider per requirement */
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if (test_bit(chan, &adc->is_divided))
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writel(1 << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET,
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adc->base + LRADC_CTRL2 + STMP_OFFSET_REG_SET);
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else
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writel(1 << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET,
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adc->base + LRADC_CTRL2 + STMP_OFFSET_REG_CLR);
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/* Clean the slot's previous content, then set new one. */
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writel(LRADC_CTRL4_LRADCSELECT_MASK(0),
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adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_CLR);
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writel(chan, adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_SET);
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writel(0, adc->base + LRADC_CH(0));
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/* Enable the IRQ and start sampling the channel. */
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writel(LRADC_CTRL1_LRADC_IRQ_EN(0),
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adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET);
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writel(BIT(0), adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET);
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/* Wait for completion on the channel, 1 second max. */
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ret = wait_for_completion_killable_timeout(&adc->completion, HZ);
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if (!ret)
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ret = -ETIMEDOUT;
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if (ret < 0)
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goto err;
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/* Read the data. */
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*val = readl(adc->base + LRADC_CH(0)) & LRADC_CH_VALUE_MASK;
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ret = IIO_VAL_INT;
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err:
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writel(LRADC_CTRL1_LRADC_IRQ_EN(0),
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adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
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iio_device_release_direct_mode(iio_dev);
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return ret;
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}
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static int mxs_lradc_adc_read_temp(struct iio_dev *iio_dev, int *val)
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{
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int ret, min, max;
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ret = mxs_lradc_adc_read_single(iio_dev, 8, &min);
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if (ret != IIO_VAL_INT)
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return ret;
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ret = mxs_lradc_adc_read_single(iio_dev, 9, &max);
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if (ret != IIO_VAL_INT)
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return ret;
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*val = max - min;
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return IIO_VAL_INT;
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}
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static int mxs_lradc_adc_read_raw(struct iio_dev *iio_dev,
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const struct iio_chan_spec *chan,
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int *val, int *val2, long m)
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{
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struct mxs_lradc_adc *adc = iio_priv(iio_dev);
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switch (m) {
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case IIO_CHAN_INFO_RAW:
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if (chan->type == IIO_TEMP)
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return mxs_lradc_adc_read_temp(iio_dev, val);
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return mxs_lradc_adc_read_single(iio_dev, chan->channel, val);
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case IIO_CHAN_INFO_SCALE:
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if (chan->type == IIO_TEMP) {
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/*
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* From the datasheet, we have to multiply by 1.012 and
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* divide by 4
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*/
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*val = 0;
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*val2 = 253000;
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return IIO_VAL_INT_PLUS_MICRO;
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}
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*val = adc->vref_mv[chan->channel];
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*val2 = chan->scan_type.realbits -
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test_bit(chan->channel, &adc->is_divided);
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return IIO_VAL_FRACTIONAL_LOG2;
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case IIO_CHAN_INFO_OFFSET:
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if (chan->type == IIO_TEMP) {
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/*
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* The calculated value from the ADC is in Kelvin, we
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* want Celsius for hwmon so the offset is -273.15
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* The offset is applied before scaling so it is
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* actually -213.15 * 4 / 1.012 = -1079.644268
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*/
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*val = -1079;
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*val2 = 644268;
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return IIO_VAL_INT_PLUS_MICRO;
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}
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return -EINVAL;
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default:
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break;
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}
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return -EINVAL;
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}
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static int mxs_lradc_adc_write_raw(struct iio_dev *iio_dev,
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const struct iio_chan_spec *chan,
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int val, int val2, long m)
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{
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struct mxs_lradc_adc *adc = iio_priv(iio_dev);
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struct mxs_lradc_scale *scale_avail =
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adc->scale_avail[chan->channel];
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int ret;
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ret = iio_device_claim_direct_mode(iio_dev);
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if (ret)
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return ret;
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switch (m) {
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case IIO_CHAN_INFO_SCALE:
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ret = -EINVAL;
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if (val == scale_avail[MXS_LRADC_DIV_DISABLED].integer &&
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val2 == scale_avail[MXS_LRADC_DIV_DISABLED].nano) {
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/* divider by two disabled */
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clear_bit(chan->channel, &adc->is_divided);
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ret = 0;
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} else if (val == scale_avail[MXS_LRADC_DIV_ENABLED].integer &&
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val2 == scale_avail[MXS_LRADC_DIV_ENABLED].nano) {
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/* divider by two enabled */
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set_bit(chan->channel, &adc->is_divided);
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ret = 0;
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}
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break;
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default:
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ret = -EINVAL;
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break;
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}
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iio_device_release_direct_mode(iio_dev);
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return ret;
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}
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static int mxs_lradc_adc_write_raw_get_fmt(struct iio_dev *iio_dev,
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const struct iio_chan_spec *chan,
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long m)
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{
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return IIO_VAL_INT_PLUS_NANO;
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}
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static ssize_t mxs_lradc_adc_show_scale_avail(struct device *dev,
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struct device_attribute *attr,
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char *buf)
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{
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struct iio_dev *iio = dev_to_iio_dev(dev);
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struct mxs_lradc_adc *adc = iio_priv(iio);
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struct iio_dev_attr *iio_attr = to_iio_dev_attr(attr);
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int i, ch, len = 0;
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ch = iio_attr->address;
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for (i = 0; i < ARRAY_SIZE(adc->scale_avail[ch]); i++)
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len += sprintf(buf + len, "%u.%09u ",
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adc->scale_avail[ch][i].integer,
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adc->scale_avail[ch][i].nano);
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len += sprintf(buf + len, "\n");
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return len;
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}
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#define SHOW_SCALE_AVAILABLE_ATTR(ch)\
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IIO_DEVICE_ATTR(in_voltage##ch##_scale_available, 0444,\
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mxs_lradc_adc_show_scale_avail, NULL, ch)
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SHOW_SCALE_AVAILABLE_ATTR(0);
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SHOW_SCALE_AVAILABLE_ATTR(1);
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SHOW_SCALE_AVAILABLE_ATTR(2);
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SHOW_SCALE_AVAILABLE_ATTR(3);
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SHOW_SCALE_AVAILABLE_ATTR(4);
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SHOW_SCALE_AVAILABLE_ATTR(5);
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SHOW_SCALE_AVAILABLE_ATTR(6);
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SHOW_SCALE_AVAILABLE_ATTR(7);
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SHOW_SCALE_AVAILABLE_ATTR(10);
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SHOW_SCALE_AVAILABLE_ATTR(11);
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SHOW_SCALE_AVAILABLE_ATTR(12);
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SHOW_SCALE_AVAILABLE_ATTR(13);
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SHOW_SCALE_AVAILABLE_ATTR(14);
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SHOW_SCALE_AVAILABLE_ATTR(15);
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static struct attribute *mxs_lradc_adc_attributes[] = {
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&iio_dev_attr_in_voltage0_scale_available.dev_attr.attr,
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&iio_dev_attr_in_voltage1_scale_available.dev_attr.attr,
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&iio_dev_attr_in_voltage2_scale_available.dev_attr.attr,
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&iio_dev_attr_in_voltage3_scale_available.dev_attr.attr,
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&iio_dev_attr_in_voltage4_scale_available.dev_attr.attr,
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&iio_dev_attr_in_voltage5_scale_available.dev_attr.attr,
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&iio_dev_attr_in_voltage6_scale_available.dev_attr.attr,
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&iio_dev_attr_in_voltage7_scale_available.dev_attr.attr,
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&iio_dev_attr_in_voltage10_scale_available.dev_attr.attr,
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&iio_dev_attr_in_voltage11_scale_available.dev_attr.attr,
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&iio_dev_attr_in_voltage12_scale_available.dev_attr.attr,
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&iio_dev_attr_in_voltage13_scale_available.dev_attr.attr,
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&iio_dev_attr_in_voltage14_scale_available.dev_attr.attr,
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&iio_dev_attr_in_voltage15_scale_available.dev_attr.attr,
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NULL
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};
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static const struct attribute_group mxs_lradc_adc_attribute_group = {
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.attrs = mxs_lradc_adc_attributes,
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};
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static const struct iio_info mxs_lradc_adc_iio_info = {
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.driver_module = THIS_MODULE,
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.read_raw = mxs_lradc_adc_read_raw,
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.write_raw = mxs_lradc_adc_write_raw,
|
||||
.write_raw_get_fmt = mxs_lradc_adc_write_raw_get_fmt,
|
||||
.attrs = &mxs_lradc_adc_attribute_group,
|
||||
};
|
||||
|
||||
/* IRQ Handling */
|
||||
static irqreturn_t mxs_lradc_adc_handle_irq(int irq, void *data)
|
||||
{
|
||||
struct iio_dev *iio = data;
|
||||
struct mxs_lradc_adc *adc = iio_priv(iio);
|
||||
struct mxs_lradc *lradc = adc->lradc;
|
||||
unsigned long reg = readl(adc->base + LRADC_CTRL1);
|
||||
unsigned long flags;
|
||||
|
||||
if (!(reg & mxs_lradc_irq_mask(lradc)))
|
||||
return IRQ_NONE;
|
||||
|
||||
if (iio_buffer_enabled(iio)) {
|
||||
if (reg & lradc->buffer_vchans) {
|
||||
spin_lock_irqsave(&adc->lock, flags);
|
||||
iio_trigger_poll(iio->trig);
|
||||
spin_unlock_irqrestore(&adc->lock, flags);
|
||||
}
|
||||
} else if (reg & LRADC_CTRL1_LRADC_IRQ(0)) {
|
||||
complete(&adc->completion);
|
||||
}
|
||||
|
||||
writel(reg & mxs_lradc_irq_mask(lradc),
|
||||
adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
|
||||
/* Trigger handling */
|
||||
static irqreturn_t mxs_lradc_adc_trigger_handler(int irq, void *p)
|
||||
{
|
||||
struct iio_poll_func *pf = p;
|
||||
struct iio_dev *iio = pf->indio_dev;
|
||||
struct mxs_lradc_adc *adc = iio_priv(iio);
|
||||
const u32 chan_value = LRADC_CH_ACCUMULATE |
|
||||
((LRADC_DELAY_TIMER_LOOP - 1) << LRADC_CH_NUM_SAMPLES_OFFSET);
|
||||
unsigned int i, j = 0;
|
||||
|
||||
for_each_set_bit(i, iio->active_scan_mask, LRADC_MAX_TOTAL_CHANS) {
|
||||
adc->buffer[j] = readl(adc->base + LRADC_CH(j));
|
||||
writel(chan_value, adc->base + LRADC_CH(j));
|
||||
adc->buffer[j] &= LRADC_CH_VALUE_MASK;
|
||||
adc->buffer[j] /= LRADC_DELAY_TIMER_LOOP;
|
||||
j++;
|
||||
}
|
||||
|
||||
iio_push_to_buffers_with_timestamp(iio, adc->buffer, pf->timestamp);
|
||||
|
||||
iio_trigger_notify_done(iio->trig);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static int mxs_lradc_adc_configure_trigger(struct iio_trigger *trig, bool state)
|
||||
{
|
||||
struct iio_dev *iio = iio_trigger_get_drvdata(trig);
|
||||
struct mxs_lradc_adc *adc = iio_priv(iio);
|
||||
const u32 st = state ? STMP_OFFSET_REG_SET : STMP_OFFSET_REG_CLR;
|
||||
|
||||
writel(LRADC_DELAY_KICK, adc->base + (LRADC_DELAY(0) + st));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct iio_trigger_ops mxs_lradc_adc_trigger_ops = {
|
||||
.owner = THIS_MODULE,
|
||||
.set_trigger_state = &mxs_lradc_adc_configure_trigger,
|
||||
};
|
||||
|
||||
static int mxs_lradc_adc_trigger_init(struct iio_dev *iio)
|
||||
{
|
||||
int ret;
|
||||
struct iio_trigger *trig;
|
||||
struct mxs_lradc_adc *adc = iio_priv(iio);
|
||||
|
||||
trig = devm_iio_trigger_alloc(&iio->dev, "%s-dev%i", iio->name,
|
||||
iio->id);
|
||||
|
||||
trig->dev.parent = adc->dev;
|
||||
iio_trigger_set_drvdata(trig, iio);
|
||||
trig->ops = &mxs_lradc_adc_trigger_ops;
|
||||
|
||||
ret = iio_trigger_register(trig);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
adc->trig = trig;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void mxs_lradc_adc_trigger_remove(struct iio_dev *iio)
|
||||
{
|
||||
struct mxs_lradc_adc *adc = iio_priv(iio);
|
||||
|
||||
iio_trigger_unregister(adc->trig);
|
||||
}
|
||||
|
||||
static int mxs_lradc_adc_buffer_preenable(struct iio_dev *iio)
|
||||
{
|
||||
struct mxs_lradc_adc *adc = iio_priv(iio);
|
||||
struct mxs_lradc *lradc = adc->lradc;
|
||||
int chan, ofs = 0;
|
||||
unsigned long enable = 0;
|
||||
u32 ctrl4_set = 0;
|
||||
u32 ctrl4_clr = 0;
|
||||
u32 ctrl1_irq = 0;
|
||||
const u32 chan_value = LRADC_CH_ACCUMULATE |
|
||||
((LRADC_DELAY_TIMER_LOOP - 1) << LRADC_CH_NUM_SAMPLES_OFFSET);
|
||||
|
||||
if (lradc->soc == IMX28_LRADC)
|
||||
writel(lradc->buffer_vchans << LRADC_CTRL1_LRADC_IRQ_EN_OFFSET,
|
||||
adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
|
||||
writel(lradc->buffer_vchans,
|
||||
adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);
|
||||
|
||||
for_each_set_bit(chan, iio->active_scan_mask, LRADC_MAX_TOTAL_CHANS) {
|
||||
ctrl4_set |= chan << LRADC_CTRL4_LRADCSELECT_OFFSET(ofs);
|
||||
ctrl4_clr |= LRADC_CTRL4_LRADCSELECT_MASK(ofs);
|
||||
ctrl1_irq |= LRADC_CTRL1_LRADC_IRQ_EN(ofs);
|
||||
writel(chan_value, adc->base + LRADC_CH(ofs));
|
||||
bitmap_set(&enable, ofs, 1);
|
||||
ofs++;
|
||||
}
|
||||
|
||||
writel(LRADC_DELAY_TRIGGER_LRADCS_MASK | LRADC_DELAY_KICK,
|
||||
adc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_CLR);
|
||||
writel(ctrl4_clr, adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_CLR);
|
||||
writel(ctrl4_set, adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_SET);
|
||||
writel(ctrl1_irq, adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET);
|
||||
writel(enable << LRADC_DELAY_TRIGGER_LRADCS_OFFSET,
|
||||
adc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_SET);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mxs_lradc_adc_buffer_postdisable(struct iio_dev *iio)
|
||||
{
|
||||
struct mxs_lradc_adc *adc = iio_priv(iio);
|
||||
struct mxs_lradc *lradc = adc->lradc;
|
||||
|
||||
writel(LRADC_DELAY_TRIGGER_LRADCS_MASK | LRADC_DELAY_KICK,
|
||||
adc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_CLR);
|
||||
|
||||
writel(lradc->buffer_vchans,
|
||||
adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);
|
||||
if (lradc->soc == IMX28_LRADC)
|
||||
writel(lradc->buffer_vchans << LRADC_CTRL1_LRADC_IRQ_EN_OFFSET,
|
||||
adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static bool mxs_lradc_adc_validate_scan_mask(struct iio_dev *iio,
|
||||
const unsigned long *mask)
|
||||
{
|
||||
struct mxs_lradc_adc *adc = iio_priv(iio);
|
||||
struct mxs_lradc *lradc = adc->lradc;
|
||||
const int map_chans = bitmap_weight(mask, LRADC_MAX_TOTAL_CHANS);
|
||||
int rsvd_chans = 0;
|
||||
unsigned long rsvd_mask = 0;
|
||||
|
||||
if (lradc->use_touchbutton)
|
||||
rsvd_mask |= CHAN_MASK_TOUCHBUTTON;
|
||||
if (lradc->touchscreen_wire == MXS_LRADC_TOUCHSCREEN_4WIRE)
|
||||
rsvd_mask |= CHAN_MASK_TOUCHSCREEN_4WIRE;
|
||||
if (lradc->touchscreen_wire == MXS_LRADC_TOUCHSCREEN_5WIRE)
|
||||
rsvd_mask |= CHAN_MASK_TOUCHSCREEN_5WIRE;
|
||||
|
||||
if (lradc->use_touchbutton)
|
||||
rsvd_chans++;
|
||||
if (lradc->touchscreen_wire)
|
||||
rsvd_chans += 2;
|
||||
|
||||
/* Test for attempts to map channels with special mode of operation. */
|
||||
if (bitmap_intersects(mask, &rsvd_mask, LRADC_MAX_TOTAL_CHANS))
|
||||
return false;
|
||||
|
||||
/* Test for attempts to map more channels then available slots. */
|
||||
if (map_chans + rsvd_chans > LRADC_MAX_MAPPED_CHANS)
|
||||
return false;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static const struct iio_buffer_setup_ops mxs_lradc_adc_buffer_ops = {
|
||||
.preenable = &mxs_lradc_adc_buffer_preenable,
|
||||
.postenable = &iio_triggered_buffer_postenable,
|
||||
.predisable = &iio_triggered_buffer_predisable,
|
||||
.postdisable = &mxs_lradc_adc_buffer_postdisable,
|
||||
.validate_scan_mask = &mxs_lradc_adc_validate_scan_mask,
|
||||
};
|
||||
|
||||
/* Driver initialization */
|
||||
#define MXS_ADC_CHAN(idx, chan_type, name) { \
|
||||
.type = (chan_type), \
|
||||
.indexed = 1, \
|
||||
.scan_index = (idx), \
|
||||
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
|
||||
BIT(IIO_CHAN_INFO_SCALE), \
|
||||
.channel = (idx), \
|
||||
.address = (idx), \
|
||||
.scan_type = { \
|
||||
.sign = 'u', \
|
||||
.realbits = LRADC_RESOLUTION, \
|
||||
.storagebits = 32, \
|
||||
}, \
|
||||
.datasheet_name = (name), \
|
||||
}
|
||||
|
||||
static const struct iio_chan_spec mx23_lradc_chan_spec[] = {
|
||||
MXS_ADC_CHAN(0, IIO_VOLTAGE, "LRADC0"),
|
||||
MXS_ADC_CHAN(1, IIO_VOLTAGE, "LRADC1"),
|
||||
MXS_ADC_CHAN(2, IIO_VOLTAGE, "LRADC2"),
|
||||
MXS_ADC_CHAN(3, IIO_VOLTAGE, "LRADC3"),
|
||||
MXS_ADC_CHAN(4, IIO_VOLTAGE, "LRADC4"),
|
||||
MXS_ADC_CHAN(5, IIO_VOLTAGE, "LRADC5"),
|
||||
MXS_ADC_CHAN(6, IIO_VOLTAGE, "VDDIO"),
|
||||
MXS_ADC_CHAN(7, IIO_VOLTAGE, "VBATT"),
|
||||
/* Combined Temperature sensors */
|
||||
{
|
||||
.type = IIO_TEMP,
|
||||
.indexed = 1,
|
||||
.scan_index = 8,
|
||||
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
|
||||
BIT(IIO_CHAN_INFO_OFFSET) |
|
||||
BIT(IIO_CHAN_INFO_SCALE),
|
||||
.channel = 8,
|
||||
.scan_type = {.sign = 'u', .realbits = 18, .storagebits = 32,},
|
||||
.datasheet_name = "TEMP_DIE",
|
||||
},
|
||||
/* Hidden channel to keep indexes */
|
||||
{
|
||||
.type = IIO_TEMP,
|
||||
.indexed = 1,
|
||||
.scan_index = -1,
|
||||
.channel = 9,
|
||||
},
|
||||
MXS_ADC_CHAN(10, IIO_VOLTAGE, NULL),
|
||||
MXS_ADC_CHAN(11, IIO_VOLTAGE, NULL),
|
||||
MXS_ADC_CHAN(12, IIO_VOLTAGE, "USB_DP"),
|
||||
MXS_ADC_CHAN(13, IIO_VOLTAGE, "USB_DN"),
|
||||
MXS_ADC_CHAN(14, IIO_VOLTAGE, "VBG"),
|
||||
MXS_ADC_CHAN(15, IIO_VOLTAGE, "VDD5V"),
|
||||
};
|
||||
|
||||
static const struct iio_chan_spec mx28_lradc_chan_spec[] = {
|
||||
MXS_ADC_CHAN(0, IIO_VOLTAGE, "LRADC0"),
|
||||
MXS_ADC_CHAN(1, IIO_VOLTAGE, "LRADC1"),
|
||||
MXS_ADC_CHAN(2, IIO_VOLTAGE, "LRADC2"),
|
||||
MXS_ADC_CHAN(3, IIO_VOLTAGE, "LRADC3"),
|
||||
MXS_ADC_CHAN(4, IIO_VOLTAGE, "LRADC4"),
|
||||
MXS_ADC_CHAN(5, IIO_VOLTAGE, "LRADC5"),
|
||||
MXS_ADC_CHAN(6, IIO_VOLTAGE, "LRADC6"),
|
||||
MXS_ADC_CHAN(7, IIO_VOLTAGE, "VBATT"),
|
||||
/* Combined Temperature sensors */
|
||||
{
|
||||
.type = IIO_TEMP,
|
||||
.indexed = 1,
|
||||
.scan_index = 8,
|
||||
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
|
||||
BIT(IIO_CHAN_INFO_OFFSET) |
|
||||
BIT(IIO_CHAN_INFO_SCALE),
|
||||
.channel = 8,
|
||||
.scan_type = {.sign = 'u', .realbits = 18, .storagebits = 32,},
|
||||
.datasheet_name = "TEMP_DIE",
|
||||
},
|
||||
/* Hidden channel to keep indexes */
|
||||
{
|
||||
.type = IIO_TEMP,
|
||||
.indexed = 1,
|
||||
.scan_index = -1,
|
||||
.channel = 9,
|
||||
},
|
||||
MXS_ADC_CHAN(10, IIO_VOLTAGE, "VDDIO"),
|
||||
MXS_ADC_CHAN(11, IIO_VOLTAGE, "VTH"),
|
||||
MXS_ADC_CHAN(12, IIO_VOLTAGE, "VDDA"),
|
||||
MXS_ADC_CHAN(13, IIO_VOLTAGE, "VDDD"),
|
||||
MXS_ADC_CHAN(14, IIO_VOLTAGE, "VBG"),
|
||||
MXS_ADC_CHAN(15, IIO_VOLTAGE, "VDD5V"),
|
||||
};
|
||||
|
||||
static void mxs_lradc_adc_hw_init(struct mxs_lradc_adc *adc)
|
||||
{
|
||||
/* The ADC always uses DELAY CHANNEL 0. */
|
||||
const u32 adc_cfg =
|
||||
(1 << (LRADC_DELAY_TRIGGER_DELAYS_OFFSET + 0)) |
|
||||
(LRADC_DELAY_TIMER_PER << LRADC_DELAY_DELAY_OFFSET);
|
||||
|
||||
/* Configure DELAY CHANNEL 0 for generic ADC sampling. */
|
||||
writel(adc_cfg, adc->base + LRADC_DELAY(0));
|
||||
|
||||
/*
|
||||
* Start internal temperature sensing by clearing bit
|
||||
* HW_LRADC_CTRL2_TEMPSENSE_PWD. This bit can be left cleared
|
||||
* after power up.
|
||||
*/
|
||||
writel(0, adc->base + LRADC_CTRL2);
|
||||
}
|
||||
|
||||
static void mxs_lradc_adc_hw_stop(struct mxs_lradc_adc *adc)
|
||||
{
|
||||
writel(0, adc->base + LRADC_DELAY(0));
|
||||
}
|
||||
|
||||
static int mxs_lradc_adc_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct mxs_lradc *lradc = dev_get_drvdata(dev->parent);
|
||||
struct mxs_lradc_adc *adc;
|
||||
struct iio_dev *iio;
|
||||
struct resource *iores;
|
||||
int ret, irq, virq, i, s, n;
|
||||
u64 scale_uv;
|
||||
const char **irq_name;
|
||||
|
||||
/* Allocate the IIO device. */
|
||||
iio = devm_iio_device_alloc(dev, sizeof(*adc));
|
||||
if (!iio) {
|
||||
dev_err(dev, "Failed to allocate IIO device\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
adc = iio_priv(iio);
|
||||
adc->lradc = lradc;
|
||||
adc->dev = dev;
|
||||
|
||||
iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
adc->base = devm_ioremap(dev, iores->start, resource_size(iores));
|
||||
if (IS_ERR(adc->base))
|
||||
return PTR_ERR(adc->base);
|
||||
|
||||
init_completion(&adc->completion);
|
||||
spin_lock_init(&adc->lock);
|
||||
|
||||
platform_set_drvdata(pdev, iio);
|
||||
|
||||
iio->name = pdev->name;
|
||||
iio->dev.parent = dev;
|
||||
iio->dev.of_node = dev->parent->of_node;
|
||||
iio->info = &mxs_lradc_adc_iio_info;
|
||||
iio->modes = INDIO_DIRECT_MODE;
|
||||
iio->masklength = LRADC_MAX_TOTAL_CHANS;
|
||||
|
||||
if (lradc->soc == IMX23_LRADC) {
|
||||
iio->channels = mx23_lradc_chan_spec;
|
||||
iio->num_channels = ARRAY_SIZE(mx23_lradc_chan_spec);
|
||||
irq_name = mx23_lradc_adc_irq_names;
|
||||
n = ARRAY_SIZE(mx23_lradc_adc_irq_names);
|
||||
} else {
|
||||
iio->channels = mx28_lradc_chan_spec;
|
||||
iio->num_channels = ARRAY_SIZE(mx28_lradc_chan_spec);
|
||||
irq_name = mx28_lradc_adc_irq_names;
|
||||
n = ARRAY_SIZE(mx28_lradc_adc_irq_names);
|
||||
}
|
||||
|
||||
ret = stmp_reset_block(adc->base);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
for (i = 0; i < n; i++) {
|
||||
irq = platform_get_irq_byname(pdev, irq_name[i]);
|
||||
if (irq < 0)
|
||||
return irq;
|
||||
|
||||
virq = irq_of_parse_and_map(dev->parent->of_node, irq);
|
||||
|
||||
ret = devm_request_irq(dev, virq, mxs_lradc_adc_handle_irq,
|
||||
0, irq_name[i], iio);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = mxs_lradc_adc_trigger_init(iio);
|
||||
if (ret)
|
||||
goto err_trig;
|
||||
|
||||
ret = iio_triggered_buffer_setup(iio, &iio_pollfunc_store_time,
|
||||
&mxs_lradc_adc_trigger_handler,
|
||||
&mxs_lradc_adc_buffer_ops);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
adc->vref_mv = mxs_lradc_adc_vref_mv[lradc->soc];
|
||||
|
||||
/* Populate available ADC input ranges */
|
||||
for (i = 0; i < LRADC_MAX_TOTAL_CHANS; i++) {
|
||||
for (s = 0; s < ARRAY_SIZE(adc->scale_avail[i]); s++) {
|
||||
/*
|
||||
* [s=0] = optional divider by two disabled (default)
|
||||
* [s=1] = optional divider by two enabled
|
||||
*
|
||||
* The scale is calculated by doing:
|
||||
* Vref >> (realbits - s)
|
||||
* which multiplies by two on the second component
|
||||
* of the array.
|
||||
*/
|
||||
scale_uv = ((u64)adc->vref_mv[i] * 100000000) >>
|
||||
(LRADC_RESOLUTION - s);
|
||||
adc->scale_avail[i][s].nano =
|
||||
do_div(scale_uv, 100000000) * 10;
|
||||
adc->scale_avail[i][s].integer = scale_uv;
|
||||
}
|
||||
}
|
||||
|
||||
/* Configure the hardware. */
|
||||
mxs_lradc_adc_hw_init(adc);
|
||||
|
||||
/* Register IIO device. */
|
||||
ret = iio_device_register(iio);
|
||||
if (ret) {
|
||||
dev_err(dev, "Failed to register IIO device\n");
|
||||
goto err_dev;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err_dev:
|
||||
mxs_lradc_adc_hw_stop(adc);
|
||||
mxs_lradc_adc_trigger_remove(iio);
|
||||
err_trig:
|
||||
iio_triggered_buffer_cleanup(iio);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int mxs_lradc_adc_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct iio_dev *iio = platform_get_drvdata(pdev);
|
||||
struct mxs_lradc_adc *adc = iio_priv(iio);
|
||||
|
||||
iio_device_unregister(iio);
|
||||
mxs_lradc_adc_hw_stop(adc);
|
||||
mxs_lradc_adc_trigger_remove(iio);
|
||||
iio_triggered_buffer_cleanup(iio);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver mxs_lradc_adc_driver = {
|
||||
.driver = {
|
||||
.name = "mxs-lradc-adc",
|
||||
},
|
||||
.probe = mxs_lradc_adc_probe,
|
||||
.remove = mxs_lradc_adc_remove,
|
||||
};
|
||||
module_platform_driver(mxs_lradc_adc_driver);
|
||||
|
||||
MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
|
||||
MODULE_DESCRIPTION("Freescale MXS LRADC driver general purpose ADC driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_ALIAS("platform:mxs-lradc-adc");
|
||||
Loading…
Reference in New Issue