Reset controller changes for v5.1
This adds the include/linux/reset directory to MAINTAINERS for reset specific headers and adds headers for sunxi and socfpga in there to get rid of a few extern function declarations. There is a new reset driver for the Broadcom STB reset controller and the i.MX7 system reset controller driver is extended to support i.MX8MQ as well. Finally, there is a new header with reset id constants for the Meson G12A SoC, which has a reset controller identical to Meson AXG and thus can reuse its driver and DT bindings. -----BEGIN PGP SIGNATURE----- iI0EABYIADUWIQRRO6F6WdpH1R0vGibVhaclGDdiwAUCXF2yeRcccC56YWJlbEBw ZW5ndXRyb25peC5kZQAKCRDVhaclGDdiwH8jAP9OQaMl5llVXuHSFOwiqkJ2I09p oROxu3dI/A4q7d5T8QD/Xuo4piSAdoT5YZyHp16NUafW3L1//wqTvxk0ubeTsgA= =EIyo -----END PGP SIGNATURE----- Merge tag 'reset-for-5.1' of git://git.pengutronix.de/git/pza/linux into arm/drivers Reset controller changes for v5.1 This adds the include/linux/reset directory to MAINTAINERS for reset specific headers and adds headers for sunxi and socfpga in there to get rid of a few extern function declarations. There is a new reset driver for the Broadcom STB reset controller and the i.MX7 system reset controller driver is extended to support i.MX8MQ as well. Finally, there is a new header with reset id constants for the Meson G12A SoC, which has a reset controller identical to Meson AXG and thus can reuse its driver and DT bindings. * tag 'reset-for-5.1' of git://git.pengutronix.de/git/pza/linux: dt-bindings: reset: meson: add g12a bindings reset: imx7: Add support for i.MX8MQ IP block variant reset: imx7: Add plubming to support multiple IP variants reset: Add Broadcom STB SW_INIT reset controller driver dt-bindings: reset: Add document for Broadcom STB reset controller reset: socfpga: declare socfpga_reset_init in a header file reset: sunxi: declare sun6i_reset_init in a header file MAINTAINERS: use include/linux/reset for reset controller related headers dt-bindings: reset: imx7: Document usage on i.MX8MQ SoCs Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
6f2185f8e3
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@ -0,0 +1,27 @@
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Broadcom STB SW_INIT-style reset controller
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===========================================
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Broadcom STB SoCs have a SW_INIT-style reset controller with separate
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SET/CLEAR/STATUS registers and possibly multiple banks, each of 32 bit
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reset lines.
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Please also refer to reset.txt in this directory for common reset
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controller binding usage.
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Required properties:
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- compatible: should be brcm,brcmstb-reset
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- reg: register base and length
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- #reset-cells: must be set to 1
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Example:
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reset: reset-controller@8404318 {
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compatible = "brcm,brcmstb-reset";
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reg = <0x8404318 0x30>;
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#reset-cells = <1>;
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};
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ðernet_switch {
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resets = <&reset>;
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reset-names = "switch";
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};
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@ -5,7 +5,9 @@ Please also refer to reset.txt in this directory for common reset
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controller binding usage.
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Required properties:
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- compatible: Should be "fsl,imx7d-src", "syscon"
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- compatible:
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- For i.MX7 SoCs should be "fsl,imx7d-src", "syscon"
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- For i.MX8MQ SoCs should be "fsl,imx8mq-src", "syscon"
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- reg: should be register base and length as documented in the
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datasheet
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- interrupts: Should contain SRC interrupt
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@ -44,4 +46,5 @@ Example:
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For list of all valid reset indicies see
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<dt-bindings/reset/imx7-reset.h>
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<dt-bindings/reset/imx7-reset.h> for i.MX7 and
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<dt-bindings/reset/imx8mq-reset.h> for i.MX8MQ
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@ -12958,6 +12958,7 @@ F: drivers/reset/
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F: Documentation/devicetree/bindings/reset/
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F: include/dt-bindings/reset/
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F: include/linux/reset.h
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F: include/linux/reset/
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F: include/linux/reset-controller.h
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RESTARTABLE SEQUENCES SUPPORT
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@ -19,6 +19,7 @@
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/reboot.h>
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#include <linux/reset/socfpga.h>
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#include <asm/hardware/cache-l2x0.h>
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#include <asm/mach/arch.h>
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@ -32,8 +33,6 @@ void __iomem *rst_manager_base_addr;
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void __iomem *sdr_ctl_base_addr;
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unsigned long socfpga_cpu1start_addr;
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extern void __init socfpga_reset_init(void);
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static void __init socfpga_sysmgr_init(void)
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{
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struct device_node *np;
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@ -14,6 +14,7 @@
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#include <linux/clocksource.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/reset/sunxi.h>
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#include <asm/mach/arch.h>
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#include <asm/secure_cntvoff.h>
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@ -37,7 +38,6 @@ static const char * const sun6i_board_dt_compat[] = {
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NULL,
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};
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extern void __init sun6i_reset_init(void);
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static void __init sun6i_timer_init(void)
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{
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of_clk_init(NULL);
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@ -40,6 +40,14 @@ config RESET_BERLIN
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help
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This enables the reset controller driver for Marvell Berlin SoCs.
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config RESET_BRCMSTB
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tristate "Broadcom STB reset controller"
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depends on ARCH_BRCMSTB || COMPILE_TEST
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default ARCH_BRCMSTB
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help
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This enables the reset controller driver for Broadcom STB SoCs using
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a SUN_TOP_CTRL_SW_INIT style controller.
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config RESET_HSDK
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bool "Synopsys HSDK Reset Driver"
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depends on HAS_IOMEM
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@ -48,9 +56,9 @@ config RESET_HSDK
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This enables the reset controller driver for HSDK board.
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config RESET_IMX7
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bool "i.MX7 Reset Driver" if COMPILE_TEST
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bool "i.MX7/8 Reset Driver" if COMPILE_TEST
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depends on HAS_IOMEM
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default SOC_IMX7D
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default SOC_IMX7D || (ARM64 && ARCH_MXC)
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select MFD_SYSCON
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help
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This enables the reset controller driver for i.MX7 SoCs.
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@ -7,6 +7,7 @@ obj-$(CONFIG_RESET_A10SR) += reset-a10sr.o
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obj-$(CONFIG_RESET_ATH79) += reset-ath79.o
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obj-$(CONFIG_RESET_AXS10X) += reset-axs10x.o
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obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o
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obj-$(CONFIG_RESET_BRCMSTB) += reset-brcmstb.o
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obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o
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obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
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obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o
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@ -0,0 +1,132 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Broadcom STB generic reset controller for SW_INIT style reset controller
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*
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* Author: Florian Fainelli <f.fainelli@gmail.com>
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* Copyright (C) 2018 Broadcom
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*/
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/reset-controller.h>
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#include <linux/types.h>
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struct brcmstb_reset {
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void __iomem *base;
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struct reset_controller_dev rcdev;
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};
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#define SW_INIT_SET 0x00
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#define SW_INIT_CLEAR 0x04
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#define SW_INIT_STATUS 0x08
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#define SW_INIT_BIT(id) BIT((id) & 0x1f)
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#define SW_INIT_BANK(id) ((id) >> 5)
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/* A full bank contains extra registers that we are not utilizing but still
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* qualify as a single bank.
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*/
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#define SW_INIT_BANK_SIZE 0x18
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static inline
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struct brcmstb_reset *to_brcmstb(struct reset_controller_dev *rcdev)
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{
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return container_of(rcdev, struct brcmstb_reset, rcdev);
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}
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static int brcmstb_reset_assert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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unsigned int off = SW_INIT_BANK(id) * SW_INIT_BANK_SIZE;
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struct brcmstb_reset *priv = to_brcmstb(rcdev);
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writel_relaxed(SW_INIT_BIT(id), priv->base + off + SW_INIT_SET);
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return 0;
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}
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static int brcmstb_reset_deassert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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unsigned int off = SW_INIT_BANK(id) * SW_INIT_BANK_SIZE;
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struct brcmstb_reset *priv = to_brcmstb(rcdev);
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writel_relaxed(SW_INIT_BIT(id), priv->base + off + SW_INIT_CLEAR);
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/* Maximum reset delay after de-asserting a line and seeing block
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* operation is typically 14us for the worst case, build some slack
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* here.
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*/
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usleep_range(100, 200);
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return 0;
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}
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static int brcmstb_reset_status(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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unsigned int off = SW_INIT_BANK(id) * SW_INIT_BANK_SIZE;
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struct brcmstb_reset *priv = to_brcmstb(rcdev);
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return readl_relaxed(priv->base + off + SW_INIT_STATUS) &
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SW_INIT_BIT(id);
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}
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static const struct reset_control_ops brcmstb_reset_ops = {
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.assert = brcmstb_reset_assert,
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.deassert = brcmstb_reset_deassert,
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.status = brcmstb_reset_status,
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};
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static int brcmstb_reset_probe(struct platform_device *pdev)
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{
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struct device *kdev = &pdev->dev;
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struct brcmstb_reset *priv;
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struct resource *res;
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priv = devm_kzalloc(kdev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!IS_ALIGNED(res->start, SW_INIT_BANK_SIZE) ||
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!IS_ALIGNED(resource_size(res), SW_INIT_BANK_SIZE)) {
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dev_err(kdev, "incorrect register range\n");
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return -EINVAL;
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}
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priv->base = devm_ioremap_resource(kdev, res);
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if (IS_ERR(priv->base))
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return PTR_ERR(priv->base);
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dev_set_drvdata(kdev, priv);
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priv->rcdev.owner = THIS_MODULE;
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priv->rcdev.nr_resets = DIV_ROUND_DOWN_ULL(resource_size(res),
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SW_INIT_BANK_SIZE) * 32;
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priv->rcdev.ops = &brcmstb_reset_ops;
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priv->rcdev.of_node = kdev->of_node;
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/* Use defaults: 1 cell and simple xlate function */
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return devm_reset_controller_register(kdev, &priv->rcdev);
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}
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static const struct of_device_id brcmstb_reset_of_match[] = {
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{ .compatible = "brcm,brcmstb-reset" },
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{ /* sentinel */ }
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};
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static struct platform_driver brcmstb_reset_driver = {
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.probe = brcmstb_reset_probe,
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.driver = {
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.name = "brcmstb-reset",
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.of_match_table = brcmstb_reset_of_match,
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},
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};
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module_platform_driver(brcmstb_reset_driver);
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MODULE_AUTHOR("Broadcom");
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MODULE_DESCRIPTION("Broadcom STB reset controller");
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MODULE_LICENSE("GPL");
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@ -17,14 +17,27 @@
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#include <linux/mfd/syscon.h>
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#include <linux/mod_devicetable.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/reset-controller.h>
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#include <linux/regmap.h>
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#include <dt-bindings/reset/imx7-reset.h>
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#include <dt-bindings/reset/imx8mq-reset.h>
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struct imx7_src_signal {
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unsigned int offset, bit;
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};
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struct imx7_src_variant {
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const struct imx7_src_signal *signals;
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unsigned int signals_num;
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struct reset_control_ops ops;
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};
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struct imx7_src {
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struct reset_controller_dev rcdev;
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struct regmap *regmap;
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const struct imx7_src_signal *signals;
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};
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enum imx7_src_registers {
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@ -39,9 +52,14 @@ enum imx7_src_registers {
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SRC_DDRC_RCR = 0x1000,
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};
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struct imx7_src_signal {
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unsigned int offset, bit;
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};
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static int imx7_reset_update(struct imx7_src *imx7src,
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unsigned long id, unsigned int value)
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{
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const struct imx7_src_signal *signal = &imx7src->signals[id];
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return regmap_update_bits(imx7src->regmap,
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signal->offset, signal->bit, value);
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}
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static const struct imx7_src_signal imx7_src_signals[IMX7_RESET_NUM] = {
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[IMX7_RESET_A7_CORE_POR_RESET0] = { SRC_A7RCR0, BIT(0) },
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@ -81,8 +99,8 @@ static int imx7_reset_set(struct reset_controller_dev *rcdev,
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unsigned long id, bool assert)
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{
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struct imx7_src *imx7src = to_imx7_src(rcdev);
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const struct imx7_src_signal *signal = &imx7_src_signals[id];
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unsigned int value = assert ? signal->bit : 0;
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const unsigned int bit = imx7src->signals[id].bit;
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unsigned int value = assert ? bit : 0;
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switch (id) {
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case IMX7_RESET_PCIEPHY:
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@ -95,12 +113,11 @@ static int imx7_reset_set(struct reset_controller_dev *rcdev,
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break;
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case IMX7_RESET_PCIE_CTRL_APPS_EN:
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value = (assert) ? 0 : signal->bit;
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value = assert ? 0 : bit;
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break;
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}
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return regmap_update_bits(imx7src->regmap,
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signal->offset, signal->bit, value);
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return imx7_reset_update(imx7src, id, value);
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}
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static int imx7_reset_assert(struct reset_controller_dev *rcdev,
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@ -115,9 +132,133 @@ static int imx7_reset_deassert(struct reset_controller_dev *rcdev,
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return imx7_reset_set(rcdev, id, false);
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}
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static const struct reset_control_ops imx7_reset_ops = {
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.assert = imx7_reset_assert,
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.deassert = imx7_reset_deassert,
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static const struct imx7_src_variant variant_imx7 = {
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.signals = imx7_src_signals,
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.signals_num = ARRAY_SIZE(imx7_src_signals),
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.ops = {
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.assert = imx7_reset_assert,
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.deassert = imx7_reset_deassert,
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},
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};
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enum imx8mq_src_registers {
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SRC_A53RCR0 = 0x0004,
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SRC_HDMI_RCR = 0x0030,
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SRC_DISP_RCR = 0x0034,
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SRC_GPU_RCR = 0x0040,
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SRC_VPU_RCR = 0x0044,
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SRC_PCIE2_RCR = 0x0048,
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SRC_MIPIPHY1_RCR = 0x004c,
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SRC_MIPIPHY2_RCR = 0x0050,
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SRC_DDRC2_RCR = 0x1004,
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};
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static const struct imx7_src_signal imx8mq_src_signals[IMX8MQ_RESET_NUM] = {
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[IMX8MQ_RESET_A53_CORE_POR_RESET0] = { SRC_A53RCR0, BIT(0) },
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[IMX8MQ_RESET_A53_CORE_POR_RESET1] = { SRC_A53RCR0, BIT(1) },
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[IMX8MQ_RESET_A53_CORE_POR_RESET2] = { SRC_A53RCR0, BIT(2) },
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[IMX8MQ_RESET_A53_CORE_POR_RESET3] = { SRC_A53RCR0, BIT(3) },
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[IMX8MQ_RESET_A53_CORE_RESET0] = { SRC_A53RCR0, BIT(4) },
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[IMX8MQ_RESET_A53_CORE_RESET1] = { SRC_A53RCR0, BIT(5) },
|
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[IMX8MQ_RESET_A53_CORE_RESET2] = { SRC_A53RCR0, BIT(6) },
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[IMX8MQ_RESET_A53_CORE_RESET3] = { SRC_A53RCR0, BIT(7) },
|
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[IMX8MQ_RESET_A53_DBG_RESET0] = { SRC_A53RCR0, BIT(8) },
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[IMX8MQ_RESET_A53_DBG_RESET1] = { SRC_A53RCR0, BIT(9) },
|
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[IMX8MQ_RESET_A53_DBG_RESET2] = { SRC_A53RCR0, BIT(10) },
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[IMX8MQ_RESET_A53_DBG_RESET3] = { SRC_A53RCR0, BIT(11) },
|
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[IMX8MQ_RESET_A53_ETM_RESET0] = { SRC_A53RCR0, BIT(12) },
|
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[IMX8MQ_RESET_A53_ETM_RESET1] = { SRC_A53RCR0, BIT(13) },
|
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[IMX8MQ_RESET_A53_ETM_RESET2] = { SRC_A53RCR0, BIT(14) },
|
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[IMX8MQ_RESET_A53_ETM_RESET3] = { SRC_A53RCR0, BIT(15) },
|
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[IMX8MQ_RESET_A53_SOC_DBG_RESET] = { SRC_A53RCR0, BIT(20) },
|
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[IMX8MQ_RESET_A53_L2RESET] = { SRC_A53RCR0, BIT(21) },
|
||||
[IMX8MQ_RESET_SW_NON_SCLR_M4C_RST] = { SRC_M4RCR, BIT(0) },
|
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[IMX8MQ_RESET_OTG1_PHY_RESET] = { SRC_USBOPHY1_RCR, BIT(0) },
|
||||
[IMX8MQ_RESET_OTG2_PHY_RESET] = { SRC_USBOPHY2_RCR, BIT(0) },
|
||||
[IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N] = { SRC_MIPIPHY_RCR, BIT(1) },
|
||||
[IMX8MQ_RESET_MIPI_DSI_RESET_N] = { SRC_MIPIPHY_RCR, BIT(2) },
|
||||
[IMX8MQ_RESET_MIPI_DIS_DPI_RESET_N] = { SRC_MIPIPHY_RCR, BIT(3) },
|
||||
[IMX8MQ_RESET_MIPI_DIS_ESC_RESET_N] = { SRC_MIPIPHY_RCR, BIT(4) },
|
||||
[IMX8MQ_RESET_MIPI_DIS_PCLK_RESET_N] = { SRC_MIPIPHY_RCR, BIT(5) },
|
||||
[IMX8MQ_RESET_PCIEPHY] = { SRC_PCIEPHY_RCR,
|
||||
BIT(2) | BIT(1) },
|
||||
[IMX8MQ_RESET_PCIEPHY_PERST] = { SRC_PCIEPHY_RCR, BIT(3) },
|
||||
[IMX8MQ_RESET_PCIE_CTRL_APPS_EN] = { SRC_PCIEPHY_RCR, BIT(6) },
|
||||
[IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF] = { SRC_PCIEPHY_RCR, BIT(11) },
|
||||
[IMX8MQ_RESET_HDMI_PHY_APB_RESET] = { SRC_HDMI_RCR, BIT(0) },
|
||||
[IMX8MQ_RESET_DISP_RESET] = { SRC_DISP_RCR, BIT(0) },
|
||||
[IMX8MQ_RESET_GPU_RESET] = { SRC_GPU_RCR, BIT(0) },
|
||||
[IMX8MQ_RESET_VPU_RESET] = { SRC_VPU_RCR, BIT(0) },
|
||||
[IMX8MQ_RESET_PCIEPHY2] = { SRC_PCIE2_RCR,
|
||||
BIT(2) | BIT(1) },
|
||||
[IMX8MQ_RESET_PCIEPHY2_PERST] = { SRC_PCIE2_RCR, BIT(3) },
|
||||
[IMX8MQ_RESET_PCIE2_CTRL_APPS_EN] = { SRC_PCIE2_RCR, BIT(6) },
|
||||
[IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF] = { SRC_PCIE2_RCR, BIT(11) },
|
||||
[IMX8MQ_RESET_MIPI_CSI1_CORE_RESET] = { SRC_MIPIPHY1_RCR, BIT(0) },
|
||||
[IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET] = { SRC_MIPIPHY1_RCR, BIT(1) },
|
||||
[IMX8MQ_RESET_MIPI_CSI1_ESC_RESET] = { SRC_MIPIPHY1_RCR, BIT(2) },
|
||||
[IMX8MQ_RESET_MIPI_CSI2_CORE_RESET] = { SRC_MIPIPHY2_RCR, BIT(0) },
|
||||
[IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET] = { SRC_MIPIPHY2_RCR, BIT(1) },
|
||||
[IMX8MQ_RESET_MIPI_CSI2_ESC_RESET] = { SRC_MIPIPHY2_RCR, BIT(2) },
|
||||
[IMX8MQ_RESET_DDRC1_PRST] = { SRC_DDRC_RCR, BIT(0) },
|
||||
[IMX8MQ_RESET_DDRC1_CORE_RESET] = { SRC_DDRC_RCR, BIT(1) },
|
||||
[IMX8MQ_RESET_DDRC1_PHY_RESET] = { SRC_DDRC_RCR, BIT(2) },
|
||||
[IMX8MQ_RESET_DDRC2_PHY_RESET] = { SRC_DDRC2_RCR, BIT(0) },
|
||||
[IMX8MQ_RESET_DDRC2_CORE_RESET] = { SRC_DDRC2_RCR, BIT(1) },
|
||||
[IMX8MQ_RESET_DDRC2_PRST] = { SRC_DDRC2_RCR, BIT(2) },
|
||||
};
|
||||
|
||||
static int imx8mq_reset_set(struct reset_controller_dev *rcdev,
|
||||
unsigned long id, bool assert)
|
||||
{
|
||||
struct imx7_src *imx7src = to_imx7_src(rcdev);
|
||||
const unsigned int bit = imx7src->signals[id].bit;
|
||||
unsigned int value = assert ? bit : 0;
|
||||
|
||||
switch (id) {
|
||||
case IMX8MQ_RESET_PCIEPHY:
|
||||
case IMX8MQ_RESET_PCIEPHY2: /* fallthrough */
|
||||
/*
|
||||
* wait for more than 10us to release phy g_rst and
|
||||
* btnrst
|
||||
*/
|
||||
if (!assert)
|
||||
udelay(10);
|
||||
break;
|
||||
|
||||
case IMX8MQ_RESET_PCIE_CTRL_APPS_EN:
|
||||
case IMX8MQ_RESET_PCIE2_CTRL_APPS_EN: /* fallthrough */
|
||||
case IMX8MQ_RESET_MIPI_DIS_PCLK_RESET_N: /* fallthrough */
|
||||
case IMX8MQ_RESET_MIPI_DIS_ESC_RESET_N: /* fallthrough */
|
||||
case IMX8MQ_RESET_MIPI_DIS_DPI_RESET_N: /* fallthrough */
|
||||
case IMX8MQ_RESET_MIPI_DSI_RESET_N: /* fallthrough */
|
||||
case IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N: /* fallthrough */
|
||||
value = assert ? 0 : bit;
|
||||
break;
|
||||
}
|
||||
|
||||
return imx7_reset_update(imx7src, id, value);
|
||||
}
|
||||
|
||||
static int imx8mq_reset_assert(struct reset_controller_dev *rcdev,
|
||||
unsigned long id)
|
||||
{
|
||||
return imx8mq_reset_set(rcdev, id, true);
|
||||
}
|
||||
|
||||
static int imx8mq_reset_deassert(struct reset_controller_dev *rcdev,
|
||||
unsigned long id)
|
||||
{
|
||||
return imx8mq_reset_set(rcdev, id, false);
|
||||
}
|
||||
|
||||
static const struct imx7_src_variant variant_imx8mq = {
|
||||
.signals = imx8mq_src_signals,
|
||||
.signals_num = ARRAY_SIZE(imx8mq_src_signals),
|
||||
.ops = {
|
||||
.assert = imx8mq_reset_assert,
|
||||
.deassert = imx8mq_reset_deassert,
|
||||
},
|
||||
};
|
||||
|
||||
static int imx7_reset_probe(struct platform_device *pdev)
|
||||
|
|
@ -125,11 +266,13 @@ static int imx7_reset_probe(struct platform_device *pdev)
|
|||
struct imx7_src *imx7src;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct regmap_config config = { .name = "src" };
|
||||
const struct imx7_src_variant *variant = of_device_get_match_data(dev);
|
||||
|
||||
imx7src = devm_kzalloc(dev, sizeof(*imx7src), GFP_KERNEL);
|
||||
if (!imx7src)
|
||||
return -ENOMEM;
|
||||
|
||||
imx7src->signals = variant->signals;
|
||||
imx7src->regmap = syscon_node_to_regmap(dev->of_node);
|
||||
if (IS_ERR(imx7src->regmap)) {
|
||||
dev_err(dev, "Unable to get imx7-src regmap");
|
||||
|
|
@ -138,15 +281,16 @@ static int imx7_reset_probe(struct platform_device *pdev)
|
|||
regmap_attach_dev(dev, imx7src->regmap, &config);
|
||||
|
||||
imx7src->rcdev.owner = THIS_MODULE;
|
||||
imx7src->rcdev.nr_resets = IMX7_RESET_NUM;
|
||||
imx7src->rcdev.ops = &imx7_reset_ops;
|
||||
imx7src->rcdev.nr_resets = variant->signals_num;
|
||||
imx7src->rcdev.ops = &variant->ops;
|
||||
imx7src->rcdev.of_node = dev->of_node;
|
||||
|
||||
return devm_reset_controller_register(dev, &imx7src->rcdev);
|
||||
}
|
||||
|
||||
static const struct of_device_id imx7_reset_dt_ids[] = {
|
||||
{ .compatible = "fsl,imx7d-src", },
|
||||
{ .compatible = "fsl,imx7d-src", .data = &variant_imx7 },
|
||||
{ .compatible = "fsl,imx8mq-src", .data = &variant_imx8mq },
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -11,6 +11,7 @@
|
|||
#include <linux/of_address.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/reset-controller.h>
|
||||
#include <linux/reset/socfpga.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/types.h>
|
||||
|
|
@ -18,7 +19,6 @@
|
|||
#include "reset-simple.h"
|
||||
|
||||
#define SOCFPGA_NR_BANKS 8
|
||||
void __init socfpga_reset_init(void);
|
||||
|
||||
static int a10_reset_init(struct device_node *np)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -18,6 +18,7 @@
|
|||
#include <linux/of_address.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/reset-controller.h>
|
||||
#include <linux/reset/sunxi.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/types.h>
|
||||
|
|
|
|||
|
|
@ -0,0 +1,134 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
|
||||
/*
|
||||
* Copyright (c) 2019 BayLibre, SAS.
|
||||
* Author: Jerome Brunet <jbrunet@baylibre.com>
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_AMLOGIC_MESON_G12A_RESET_H
|
||||
#define _DT_BINDINGS_AMLOGIC_MESON_G12A_RESET_H
|
||||
|
||||
/* RESET0 */
|
||||
#define RESET_HIU 0
|
||||
/* 1 */
|
||||
#define RESET_DOS 2
|
||||
/* 3-4 */
|
||||
#define RESET_VIU 5
|
||||
#define RESET_AFIFO 6
|
||||
#define RESET_VID_PLL_DIV 7
|
||||
/* 8-9 */
|
||||
#define RESET_VENC 10
|
||||
#define RESET_ASSIST 11
|
||||
#define RESET_PCIE_CTRL_A 12
|
||||
#define RESET_VCBUS 13
|
||||
#define RESET_PCIE_PHY 14
|
||||
#define RESET_PCIE_APB 15
|
||||
#define RESET_GIC 16
|
||||
#define RESET_CAPB3_DECODE 17
|
||||
/* 18 */
|
||||
#define RESET_HDMITX_CAPB3 19
|
||||
#define RESET_DVALIN_CAPB3 20
|
||||
#define RESET_DOS_CAPB3 21
|
||||
/* 22 */
|
||||
#define RESET_CBUS_CAPB3 23
|
||||
#define RESET_AHB_CNTL 24
|
||||
#define RESET_AHB_DATA 25
|
||||
#define RESET_VCBUS_CLK81 26
|
||||
/* 27-31 */
|
||||
/* RESET1 */
|
||||
/* 32 */
|
||||
#define RESET_DEMUX 33
|
||||
#define RESET_USB 34
|
||||
#define RESET_DDR 35
|
||||
/* 36 */
|
||||
#define RESET_BT656 37
|
||||
#define RESET_AHB_SRAM 38
|
||||
/* 39 */
|
||||
#define RESET_PARSER 40
|
||||
/* 41 */
|
||||
#define RESET_ISA 42
|
||||
#define RESET_ETHERNET 43
|
||||
#define RESET_SD_EMMC_A 44
|
||||
#define RESET_SD_EMMC_B 45
|
||||
#define RESET_SD_EMMC_C 46
|
||||
/* 47-60 */
|
||||
#define RESET_AUDIO_CODEC 61
|
||||
/* 62-63 */
|
||||
/* RESET2 */
|
||||
/* 64 */
|
||||
#define RESET_AUDIO 65
|
||||
#define RESET_HDMITX_PHY 66
|
||||
/* 67 */
|
||||
#define RESET_MIPI_DSI_HOST 68
|
||||
#define RESET_ALOCKER 69
|
||||
#define RESET_GE2D 70
|
||||
#define RESET_PARSER_REG 71
|
||||
#define RESET_PARSER_FETCH 72
|
||||
#define RESET_CTL 73
|
||||
#define RESET_PARSER_TOP 74
|
||||
/* 75-77 */
|
||||
#define RESET_DVALIN 78
|
||||
#define RESET_HDMITX 79
|
||||
/* 80-95 */
|
||||
/* RESET3 */
|
||||
/* 96-95 */
|
||||
#define RESET_DEMUX_TOP 105
|
||||
#define RESET_DEMUX_DES_PL 106
|
||||
#define RESET_DEMUX_S2P_0 107
|
||||
#define RESET_DEMUX_S2P_1 108
|
||||
#define RESET_DEMUX_0 109
|
||||
#define RESET_DEMUX_1 110
|
||||
#define RESET_DEMUX_2 111
|
||||
/* 112-127 */
|
||||
/* RESET4 */
|
||||
/* 128-129 */
|
||||
#define RESET_MIPI_DSI_PHY 130
|
||||
/* 131-132 */
|
||||
#define RESET_RDMA 133
|
||||
#define RESET_VENCI 134
|
||||
#define RESET_VENCP 135
|
||||
/* 136 */
|
||||
#define RESET_VDAC 137
|
||||
/* 138-139 */
|
||||
#define RESET_VDI6 140
|
||||
#define RESET_VENCL 141
|
||||
#define RESET_I2C_M1 142
|
||||
#define RESET_I2C_M2 143
|
||||
/* 144-159 */
|
||||
/* RESET5 */
|
||||
/* 160-191 */
|
||||
/* RESET6 */
|
||||
#define RESET_GEN 192
|
||||
#define RESET_SPICC0 193
|
||||
#define RESET_SC 194
|
||||
#define RESET_SANA_3 195
|
||||
#define RESET_I2C_M0 196
|
||||
#define RESET_TS_PLL 197
|
||||
#define RESET_SPICC1 198
|
||||
#define RESET_STREAM 199
|
||||
#define RESET_TS_CPU 200
|
||||
#define RESET_UART0 201
|
||||
#define RESET_UART1_2 202
|
||||
#define RESET_ASYNC0 203
|
||||
#define RESET_ASYNC1 204
|
||||
#define RESET_SPIFC0 205
|
||||
#define RESET_I2C_M3 206
|
||||
/* 207-223 */
|
||||
/* RESET7 */
|
||||
#define RESET_USB_DDR_0 224
|
||||
#define RESET_USB_DDR_1 225
|
||||
#define RESET_USB_DDR_2 226
|
||||
#define RESET_USB_DDR_3 227
|
||||
#define RESET_TS_GPU 228
|
||||
#define RESET_DEVICE_MMC_ARB 229
|
||||
#define RESET_DVALIN_DMC_PIPL 230
|
||||
#define RESET_VID_LOCK 231
|
||||
#define RESET_NIC_DMC_PIPL 232
|
||||
#define RESET_DMC_VPU_PIPL 233
|
||||
#define RESET_GE2D_DMC_PIPL 234
|
||||
#define RESET_HCODEC_DMC_PIPL 235
|
||||
#define RESET_WAVE420_DMC_PIPL 236
|
||||
#define RESET_HEVCF_DMC_PIPL 237
|
||||
/* 238-255 */
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,64 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2018 Zodiac Inflight Innovations
|
||||
*
|
||||
* Author: Andrey Smirnov <andrew.smirnov@gmail.com>
|
||||
*/
|
||||
|
||||
#ifndef DT_BINDING_RESET_IMX8MQ_H
|
||||
#define DT_BINDING_RESET_IMX8MQ_H
|
||||
|
||||
#define IMX8MQ_RESET_A53_CORE_POR_RESET0 0
|
||||
#define IMX8MQ_RESET_A53_CORE_POR_RESET1 1
|
||||
#define IMX8MQ_RESET_A53_CORE_POR_RESET2 2
|
||||
#define IMX8MQ_RESET_A53_CORE_POR_RESET3 3
|
||||
#define IMX8MQ_RESET_A53_CORE_RESET0 4
|
||||
#define IMX8MQ_RESET_A53_CORE_RESET1 5
|
||||
#define IMX8MQ_RESET_A53_CORE_RESET2 6
|
||||
#define IMX8MQ_RESET_A53_CORE_RESET3 7
|
||||
#define IMX8MQ_RESET_A53_DBG_RESET0 8
|
||||
#define IMX8MQ_RESET_A53_DBG_RESET1 9
|
||||
#define IMX8MQ_RESET_A53_DBG_RESET2 10
|
||||
#define IMX8MQ_RESET_A53_DBG_RESET3 11
|
||||
#define IMX8MQ_RESET_A53_ETM_RESET0 12
|
||||
#define IMX8MQ_RESET_A53_ETM_RESET1 13
|
||||
#define IMX8MQ_RESET_A53_ETM_RESET2 14
|
||||
#define IMX8MQ_RESET_A53_ETM_RESET3 15
|
||||
#define IMX8MQ_RESET_A53_SOC_DBG_RESET 16
|
||||
#define IMX8MQ_RESET_A53_L2RESET 17
|
||||
#define IMX8MQ_RESET_SW_NON_SCLR_M4C_RST 18
|
||||
#define IMX8MQ_RESET_OTG1_PHY_RESET 19
|
||||
#define IMX8MQ_RESET_OTG2_PHY_RESET 20
|
||||
#define IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N 21
|
||||
#define IMX8MQ_RESET_MIPI_DSI_RESET_N 22
|
||||
#define IMX8MQ_RESET_MIPI_DIS_DPI_RESET_N 23
|
||||
#define IMX8MQ_RESET_MIPI_DIS_ESC_RESET_N 24
|
||||
#define IMX8MQ_RESET_MIPI_DIS_PCLK_RESET_N 25
|
||||
#define IMX8MQ_RESET_PCIEPHY 26
|
||||
#define IMX8MQ_RESET_PCIEPHY_PERST 27
|
||||
#define IMX8MQ_RESET_PCIE_CTRL_APPS_EN 28
|
||||
#define IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF 29
|
||||
#define IMX8MQ_RESET_HDMI_PHY_APB_RESET 30
|
||||
#define IMX8MQ_RESET_DISP_RESET 31
|
||||
#define IMX8MQ_RESET_GPU_RESET 32
|
||||
#define IMX8MQ_RESET_VPU_RESET 33
|
||||
#define IMX8MQ_RESET_PCIEPHY2 34
|
||||
#define IMX8MQ_RESET_PCIEPHY2_PERST 35
|
||||
#define IMX8MQ_RESET_PCIE2_CTRL_APPS_EN 36
|
||||
#define IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF 37
|
||||
#define IMX8MQ_RESET_MIPI_CSI1_CORE_RESET 38
|
||||
#define IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET 39
|
||||
#define IMX8MQ_RESET_MIPI_CSI1_ESC_RESET 40
|
||||
#define IMX8MQ_RESET_MIPI_CSI2_CORE_RESET 41
|
||||
#define IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET 42
|
||||
#define IMX8MQ_RESET_MIPI_CSI2_ESC_RESET 43
|
||||
#define IMX8MQ_RESET_DDRC1_PRST 44
|
||||
#define IMX8MQ_RESET_DDRC1_CORE_RESET 45
|
||||
#define IMX8MQ_RESET_DDRC1_PHY_RESET 46
|
||||
#define IMX8MQ_RESET_DDRC2_PRST 47
|
||||
#define IMX8MQ_RESET_DDRC2_CORE_RESET 48
|
||||
#define IMX8MQ_RESET_DDRC2_PHY_RESET 49
|
||||
|
||||
#define IMX8MQ_RESET_NUM 50
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __LINUX_RESET_SOCFPGA_H__
|
||||
#define __LINUX_RESET_SOCFPGA_H__
|
||||
|
||||
void __init socfpga_reset_init(void);
|
||||
|
||||
#endif /* __LINUX_RESET_SOCFPGA_H__ */
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __LINUX_RESET_SUNXI_H__
|
||||
#define __LINUX_RESET_SUNXI_H__
|
||||
|
||||
void __init sun6i_reset_init(void);
|
||||
|
||||
#endif /* __LINUX_RESET_SUNXI_H__ */
|
||||
Loading…
Reference in New Issue