net/macb: Fix comments to meet style guidelines
Change comments to not exceed 80 characters per line. Update block comments in macb.h to start on the line after /*. Signed-off-by: Xander Huff <xander.huff@ni.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Xander Huff
David S. Miller
parent
331b9ab80a
commit
6f79eed886
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@ -82,159 +82,52 @@
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#define GEM_SA4B 0x00A0 /* Specific4 Bottom */
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#define GEM_SA4T 0x00A4 /* Specific4 Top */
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#define GEM_OTX 0x0100 /* Octets transmitted */
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#define GEM_OCTTXL 0x0100 /* Octets transmitted
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* [31:0]
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*/
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#define GEM_OCTTXH 0x0104 /* Octets transmitted
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* [47:32]
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*/
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#define GEM_TXCNT 0x0108 /* Error-free Frames
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* Transmitted counter
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*/
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#define GEM_TXBCCNT 0x010c /* Error-free Broadcast
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* Frames counter
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*/
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#define GEM_TXMCCNT 0x0110 /* Error-free Multicast
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* Frames counter
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*/
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#define GEM_TXPAUSECNT 0x0114 /* Pause Frames
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* Transmitted Counter
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*/
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#define GEM_TX64CNT 0x0118 /* Error-free 64 byte
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* Frames Transmitted
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* counter
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*/
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#define GEM_TX65CNT 0x011c /* Error-free 65-127 byte
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* Frames Transmitted
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* counter
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*/
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#define GEM_TX128CNT 0x0120 /* Error-free 128-255
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* byte Frames
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* Transmitted counter
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*/
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#define GEM_TX256CNT 0x0124 /* Error-free 256-511
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* byte Frames
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* transmitted counter
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*/
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#define GEM_TX512CNT 0x0128 /* Error-free 512-1023
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* byte Frames
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* transmitted counter
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*/
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#define GEM_TX1024CNT 0x012c /* Error-free 1024-1518
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* byte Frames
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* transmitted counter
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*/
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#define GEM_TX1519CNT 0x0130 /* Error-free larger than
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* 1519 byte Frames
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* tranmitted counter
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*/
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#define GEM_TXURUNCNT 0x0134 /* TX under run error
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* counter
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*/
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#define GEM_SNGLCOLLCNT 0x0138 /* Single Collision Frame
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* Counter
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*/
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#define GEM_MULTICOLLCNT 0x013c /* Multiple Collision
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* Frame Counter
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*/
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#define GEM_EXCESSCOLLCNT 0x0140 /* Excessive Collision
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* Frame Counter
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*/
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#define GEM_LATECOLLCNT 0x0144 /* Late Collision Frame
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* Counter
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*/
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#define GEM_TXDEFERCNT 0x0148 /* Deferred Transmission
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* Frame Counter
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*/
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#define GEM_TXCSENSECNT 0x014c /* Carrier Sense Error
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* Counter
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*/
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#define GEM_OCTTXL 0x0100 /* Octets transmitted [31:0] */
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#define GEM_OCTTXH 0x0104 /* Octets transmitted [47:32] */
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#define GEM_TXCNT 0x0108 /* Frames Transmitted counter */
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#define GEM_TXBCCNT 0x010c /* Broadcast Frames counter */
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#define GEM_TXMCCNT 0x0110 /* Multicast Frames counter */
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#define GEM_TXPAUSECNT 0x0114 /* Pause Frames Transmitted Counter */
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#define GEM_TX64CNT 0x0118 /* 64 byte Frames TX counter */
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#define GEM_TX65CNT 0x011c /* 65-127 byte Frames TX counter */
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#define GEM_TX128CNT 0x0120 /* 128-255 byte Frames TX counter */
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#define GEM_TX256CNT 0x0124 /* 256-511 byte Frames TX counter */
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#define GEM_TX512CNT 0x0128 /* 512-1023 byte Frames TX counter */
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#define GEM_TX1024CNT 0x012c /* 1024-1518 byte Frames TX counter */
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#define GEM_TX1519CNT 0x0130 /* 1519+ byte Frames TX counter */
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#define GEM_TXURUNCNT 0x0134 /* TX under run error counter */
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#define GEM_SNGLCOLLCNT 0x0138 /* Single Collision Frame Counter */
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#define GEM_MULTICOLLCNT 0x013c /* Multiple Collision Frame Counter */
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#define GEM_EXCESSCOLLCNT 0x0140 /* Excessive Collision Frame Counter */
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#define GEM_LATECOLLCNT 0x0144 /* Late Collision Frame Counter */
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#define GEM_TXDEFERCNT 0x0148 /* Deferred Transmission Frame Counter */
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#define GEM_TXCSENSECNT 0x014c /* Carrier Sense Error Counter */
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#define GEM_ORX 0x0150 /* Octets received */
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#define GEM_OCTRXL 0x0150 /* Octets received
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* [31:0]
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*/
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#define GEM_OCTRXH 0x0154 /* Octets received
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* [47:32]
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*/
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#define GEM_RXCNT 0x0158 /* Error-free Frames
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* Received Counter
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*/
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#define GEM_RXBROADCNT 0x015c /* Error-free Broadcast
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* Frames Received
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* Counter
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*/
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#define GEM_RXMULTICNT 0x0160 /* Error-free Multicast
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* Frames Received
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* Counter
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*/
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#define GEM_RXPAUSECNT 0x0164 /* Error-free Pause
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* Frames Received
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* Counter
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*/
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#define GEM_RX64CNT 0x0168 /* Error-free 64 byte
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* Frames Received
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* Counter
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*/
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#define GEM_RX65CNT 0x016c /* Error-free 65-127 byte
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* Frames Received
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* Counter
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*/
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#define GEM_RX128CNT 0x0170 /* Error-free 128-255
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* byte Frames Received
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* Counter
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*/
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#define GEM_RX256CNT 0x0174 /* Error-free 256-511
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* byte Frames Received
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* Counter
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*/
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#define GEM_RX512CNT 0x0178 /* Error-free 512-1023
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* byte Frames Received
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* Counter
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*/
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#define GEM_RX1024CNT 0x017c /* Error-free 1024-1518
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* byte Frames Received
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* Counter
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*/
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#define GEM_RX1519CNT 0x0180 /* Error-free larger than
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* 1519 Frames Received
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* Counter
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*/
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#define GEM_RXUNDRCNT 0x0184 /* Undersize Frames
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* Received Counter
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*/
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#define GEM_RXOVRCNT 0x0188 /* Oversize Frames
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* Received Counter
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*/
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#define GEM_RXJABCNT 0x018c /* Jabbers Received
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* Counter
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*/
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#define GEM_RXFCSCNT 0x0190 /* Frame Check Sequence
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* Error Counter
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*/
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#define GEM_RXLENGTHCNT 0x0194 /* Length Field Error
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* Counter
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*/
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#define GEM_RXSYMBCNT 0x0198 /* Symbol Error
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* Counter
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*/
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#define GEM_RXALIGNCNT 0x019c /* Alignment Error
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* Counter
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*/
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#define GEM_RXRESERRCNT 0x01a0 /* Receive Resource Error
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* Counter
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*/
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#define GEM_RXORCNT 0x01a4 /* Receive Overrun
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* Counter
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*/
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#define GEM_RXIPCCNT 0x01a8 /* IP header Checksum
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* Error Counter
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*/
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#define GEM_RXTCPCCNT 0x01ac /* TCP Checksum Error
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* Counter
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*/
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#define GEM_RXUDPCCNT 0x01b0 /* UDP Checksum Error
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* Counter
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*/
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#define GEM_OCTRXL 0x0150 /* Octets received [31:0] */
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#define GEM_OCTRXH 0x0154 /* Octets received [47:32] */
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#define GEM_RXCNT 0x0158 /* Frames Received Counter */
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#define GEM_RXBROADCNT 0x015c /* Broadcast Frames Received Counter */
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#define GEM_RXMULTICNT 0x0160 /* Multicast Frames Received Counter */
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#define GEM_RXPAUSECNT 0x0164 /* Pause Frames Received Counter */
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#define GEM_RX64CNT 0x0168 /* 64 byte Frames RX Counter */
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#define GEM_RX65CNT 0x016c /* 65-127 byte Frames RX Counter */
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#define GEM_RX128CNT 0x0170 /* 128-255 byte Frames RX Counter */
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#define GEM_RX256CNT 0x0174 /* 256-511 byte Frames RX Counter */
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#define GEM_RX512CNT 0x0178 /* 512-1023 byte Frames RX Counter */
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#define GEM_RX1024CNT 0x017c /* 1024-1518 byte Frames RX Counter */
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#define GEM_RX1519CNT 0x0180 /* 1519+ byte Frames RX Counter */
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#define GEM_RXUNDRCNT 0x0184 /* Undersize Frames Received Counter */
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#define GEM_RXOVRCNT 0x0188 /* Oversize Frames Received Counter */
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#define GEM_RXJABCNT 0x018c /* Jabbers Received Counter */
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#define GEM_RXFCSCNT 0x0190 /* Frame Check Sequence Error Counter */
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#define GEM_RXLENGTHCNT 0x0194 /* Length Field Error Counter */
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#define GEM_RXSYMBCNT 0x0198 /* Symbol Error Counter */
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#define GEM_RXALIGNCNT 0x019c /* Alignment Error Counter */
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#define GEM_RXRESERRCNT 0x01a0 /* Receive Resource Error Counter */
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#define GEM_RXORCNT 0x01a4 /* Receive Overrun Counter */
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#define GEM_RXIPCCNT 0x01a8 /* IP header Checksum Error Counter */
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#define GEM_RXTCPCCNT 0x01ac /* TCP Checksum Error Counter */
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#define GEM_RXUDPCCNT 0x01b0 /* UDP Checksum Error Counter */
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#define GEM_DCFG1 0x0280 /* Design Config 1 */
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#define GEM_DCFG2 0x0284 /* Design Config 2 */
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#define GEM_DCFG3 0x0288 /* Design Config 3 */
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@ -275,9 +168,7 @@
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#define MACB_THALT_SIZE 1
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#define MACB_NCR_TPF_OFFSET 11 /* Transmit pause frame */
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#define MACB_NCR_TPF_SIZE 1
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#define MACB_TZQ_OFFSET 12 /* Transmit zero quantum
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* pause frame
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*/
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#define MACB_TZQ_OFFSET 12 /* Transmit zero quantum pause frame */
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#define MACB_TZQ_SIZE 1
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/* Bitfields in NCFGR */
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@ -299,9 +190,7 @@
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#define MACB_UNI_SIZE 1
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#define MACB_BIG_OFFSET 8 /* Receive 1536 byte frames */
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#define MACB_BIG_SIZE 1
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#define MACB_EAE_OFFSET 9 /* External address match
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* enable
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*/
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#define MACB_EAE_OFFSET 9 /* External address match enable */
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#define MACB_EAE_SIZE 1
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#define MACB_CLK_OFFSET 10
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#define MACB_CLK_SIZE 2
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@ -313,9 +202,7 @@
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#define MACB_RM9200_RMII_SIZE 1 /* AT91RM9200 only */
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#define MACB_RBOF_OFFSET 14 /* Receive buffer offset */
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#define MACB_RBOF_SIZE 2
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#define MACB_RLCE_OFFSET 16 /* Length field error frame
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* discard
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*/
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#define MACB_RLCE_OFFSET 16 /* Length field error frame discard */
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#define MACB_RLCE_SIZE 1
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#define MACB_DRFCS_OFFSET 17 /* FCS remove */
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#define MACB_DRFCS_SIZE 1
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@ -335,41 +222,22 @@
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#define GEM_RXCOEN_SIZE 1
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/* Constants for data bus width. */
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#define GEM_DBW32 0 /* 32 bit AMBA AHB data bus
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* width
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*/
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#define GEM_DBW64 1 /* 64 bit AMBA AHB data bus
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* width
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*/
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#define GEM_DBW128 2 /* 128 bit AMBA AHB data bus
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* width
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*/
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#define GEM_DBW32 0 /* 32 bit AMBA AHB data bus width */
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#define GEM_DBW64 1 /* 64 bit AMBA AHB data bus width */
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#define GEM_DBW128 2 /* 128 bit AMBA AHB data bus width */
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/* Bitfields in DMACFG. */
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#define GEM_FBLDO_OFFSET 0 /* AHB fixed burst length for
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* DMA data operations
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*/
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#define GEM_FBLDO_OFFSET 0 /* fixed burst length for DMA */
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#define GEM_FBLDO_SIZE 5
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#define GEM_ENDIA_OFFSET 7 /* AHB endian swap mode enable
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* for packet data accesses
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*/
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#define GEM_ENDIA_OFFSET 7 /* endian swap mode for packet data access */
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#define GEM_ENDIA_SIZE 1
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#define GEM_RXBMS_OFFSET 8 /* Receiver packet buffer
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* memory size select
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*/
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#define GEM_RXBMS_OFFSET 8 /* RX packet buffer memory size select */
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#define GEM_RXBMS_SIZE 2
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#define GEM_TXPBMS_OFFSET 10 /* Transmitter packet buffer
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* memory size select
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*/
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#define GEM_TXPBMS_OFFSET 10 /* TX packet buffer memory size select */
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#define GEM_TXPBMS_SIZE 1
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#define GEM_TXCOEN_OFFSET 11 /* Transmitter IP, TCP and
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* UDP checksum generation
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* offload enable
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*/
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#define GEM_TXCOEN_OFFSET 11 /* TX IP/TCP/UDP checksum gen offload */
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#define GEM_TXCOEN_SIZE 1
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#define GEM_RXBS_OFFSET 16 /* DMA receive buffer size in
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* AHB system memory
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*/
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#define GEM_RXBS_OFFSET 16 /* DMA receive buffer size */
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#define GEM_RXBS_SIZE 8
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#define GEM_DDRP_OFFSET 24 /* disc_when_no_ahb */
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#define GEM_DDRP_SIZE 1
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@ -378,13 +246,9 @@
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/* Bitfields in NSR */
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#define MACB_NSR_LINK_OFFSET 0 /* pcs_link_state */
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#define MACB_NSR_LINK_SIZE 1
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#define MACB_MDIO_OFFSET 1 /* status of the mdio_in
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* pin
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*/
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#define MACB_MDIO_OFFSET 1 /* status of the mdio_in pin */
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#define MACB_MDIO_SIZE 1
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#define MACB_IDLE_OFFSET 2 /* The PHY management logic is
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* idle (i.e. has completed)
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*/
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#define MACB_IDLE_OFFSET 2 /* The PHY management logic is idle */
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#define MACB_IDLE_SIZE 1
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/* Bitfields in TSR */
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@ -396,9 +260,7 @@
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#define MACB_TSR_RLE_SIZE 1
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#define MACB_TGO_OFFSET 3 /* Transmit go */
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#define MACB_TGO_SIZE 1
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#define MACB_BEX_OFFSET 4 /* Transmit frame corruption
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* due to AHB error
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*/
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#define MACB_BEX_OFFSET 4 /* TX frame corruption due to AHB error */
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#define MACB_BEX_SIZE 1
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#define MACB_RM9200_BNQ_OFFSET 4 /* AT91RM9200 only */
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#define MACB_RM9200_BNQ_SIZE 1 /* AT91RM9200 only */
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@ -424,43 +286,23 @@
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#define MACB_RXUBR_SIZE 1
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#define MACB_TXUBR_OFFSET 3 /* TX used bit read */
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#define MACB_TXUBR_SIZE 1
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#define MACB_ISR_TUND_OFFSET 4 /* Enable trnasmit buffer
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* under run interrupt
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*/
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#define MACB_ISR_TUND_OFFSET 4 /* Enable TX buffer under run interrupt */
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#define MACB_ISR_TUND_SIZE 1
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#define MACB_ISR_RLE_OFFSET 5 /* Enable retry limit exceeded
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* or late collision interrupt
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*/
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#define MACB_ISR_RLE_OFFSET 5 /* EN retry exceeded/late coll interrupt */
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#define MACB_ISR_RLE_SIZE 1
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#define MACB_TXERR_OFFSET 6 /* Enable transmit frame
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* corruption due to AHB error
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* interrupt
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*/
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#define MACB_TXERR_OFFSET 6 /* EN TX frame corrupt from error interrupt */
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#define MACB_TXERR_SIZE 1
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#define MACB_TCOMP_OFFSET 7 /* Enable transmit complete
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* interrupt
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*/
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#define MACB_TCOMP_OFFSET 7 /* Enable transmit complete interrupt */
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#define MACB_TCOMP_SIZE 1
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#define MACB_ISR_LINK_OFFSET 9 /* Enable link change
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* interrupt
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*/
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#define MACB_ISR_LINK_OFFSET 9 /* Enable link change interrupt */
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#define MACB_ISR_LINK_SIZE 1
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#define MACB_ISR_ROVR_OFFSET 10 /* Enable receive overrun
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* interrupt
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*/
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#define MACB_ISR_ROVR_OFFSET 10 /* Enable receive overrun interrupt */
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#define MACB_ISR_ROVR_SIZE 1
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#define MACB_HRESP_OFFSET 11 /* Enable hrsep not OK
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* interrupt
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*/
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#define MACB_HRESP_OFFSET 11 /* Enable hrsep not OK interrupt */
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#define MACB_HRESP_SIZE 1
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#define MACB_PFR_OFFSET 12 /* Enable pause frame with
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* non-zero pause quantum
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* interrupt
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*/
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#define MACB_PFR_OFFSET 12 /* Enable pause frame w/ quantum interrupt */
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#define MACB_PFR_SIZE 1
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#define MACB_PTZ_OFFSET 13 /* Enable pause time zero
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* interrupt
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*/
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#define MACB_PTZ_OFFSET 13 /* Enable pause time zero interrupt */
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#define MACB_PTZ_SIZE 1
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/* Bitfields in MAN */
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@ -472,13 +314,9 @@
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#define MACB_REGA_SIZE 5
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#define MACB_PHYA_OFFSET 23 /* PHY address */
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#define MACB_PHYA_SIZE 5
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#define MACB_RW_OFFSET 28 /* Operation. 10 is read. 01
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* is write.
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*/
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#define MACB_RW_OFFSET 28 /* Operation. 10 is read. 01 is write. */
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#define MACB_RW_SIZE 2
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#define MACB_SOF_OFFSET 30 /* Must be written to 1 for
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* Clause 22 operation
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*/
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#define MACB_SOF_OFFSET 30 /* Must be written to 1 for Clause 22 */
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#define MACB_SOF_SIZE 2
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/* Bitfields in USRIO (AVR32) */
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@ -597,8 +435,7 @@
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#define queue_writel(queue, reg, value) \
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__raw_writel((value), (queue)->bp->regs + (queue)->reg)
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/*
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* Conditional GEM/MACB macros. These perform the operation to the correct
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/* Conditional GEM/MACB macros. These perform the operation to the correct
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* register dependent on whether the device is a GEM or a MACB. For registers
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* and bitfields that are common across both devices, use macb_{read,write}l
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* to avoid the cost of the conditional.
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@ -621,8 +458,7 @@
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__v; \
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})
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/**
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* struct macb_dma_desc - Hardware DMA descriptor
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/* struct macb_dma_desc - Hardware DMA descriptor
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* @addr: DMA address of data buffer
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* @ctrl: Control and status bits
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*/
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@ -711,8 +547,7 @@ struct macb_dma_desc {
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/* limit RX checksum offload to TCP and UDP packets */
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#define GEM_RX_CSUM_CHECKED_MASK 2
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/**
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* struct macb_tx_skb - data about an skb which is being transmitted
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/* struct macb_tx_skb - data about an skb which is being transmitted
|
||||
* @skb: skb currently being transmitted, only set for the last buffer
|
||||
* of the frame
|
||||
* @mapping: DMA address of the skb's fragment buffer
|
||||
|
|
@ -727,8 +562,7 @@ struct macb_tx_skb {
|
|||
bool mapped_as_page;
|
||||
};
|
||||
|
||||
/*
|
||||
* Hardware-collected statistics. Used when updating the network
|
||||
/* Hardware-collected statistics. Used when updating the network
|
||||
* device stats by a periodic timer.
|
||||
*/
|
||||
struct macb_stats {
|
||||
|
|
|
|||
Loading…
Reference in New Issue