RISC-V updates for v5.5-rc7
Three fixes for RISC-V: - Don't free and reuse memory containing the code that CPUs parked at boot reside in. - Fix rv64 build problems for ubsan and some modules by adding logical and arithmetic shift helpers for 128-bit values. These are from libgcc and are similar to what's present for ARM64. - Fix vDSO builds to clean up their own temporary files. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEElRDoIDdEz9/svf2Kx4+xDQu9KksFAl4klXMACgkQx4+xDQu9 KkshPhAAiExCAl2JpZxoeuyQmjS7X68au5CWWJa+uB5osAgxJSPk4XJt9QeagOFw wpKmefQDwPKXQuoD0VmNSdJMioBvgzFLqftoc2D9GAv3A0MB4miSsZkUheVbUifN jtc3tc3jOCiVNOb0lbX+B6NL+qentvV6CTmujrf79wDBZpGPzKSM2S2OZMvFijVY B7ijF1bqXBZg6weE8xdefJhBfDmd7vDBKmMJtv1RUbiOgoBGqjM8QtaXVrUz4Px0 NLlTleZL4grZVCepJ4psambm5gcZ8UilAe/ywhhrSFOSNCTYKB3ST+ci9VC4t5Vx TiR6MnDV1qAl2Uh6aoOhZECpggge9zQOyER7QGbleNplxavhi6jsRgeV9hbqeyBZ FCanzqO33irRwrtl7lNsPiUv3XWyyGH5yQLxA9wPq/W9dJkO6Z8pl5Fq0kI/oJNj WtlVIp2EnkXJUmXiMBTHerLoBJAVnu+S2HRIeRqOEUSKT4bFP28kq3T6ctP4QuoT 3F2k9A3DOIZPY8dhXIdFSdcM0IbfRliFy/9hHLt6JdSa35poxGUBpOafDq87n9/3 UtbkLbxJd56EWOSx5l2bLJ/b4FjJX6powfV9cwjrHjrzoiAqc8z0lfQRGlbGjeYb 3XTTXhLIspGMK8acm8/p2I6uwDVGFMveEdsLJ8UWAiYjJkLSFEk= =SfqL -----END PGP SIGNATURE----- Merge tag 'riscv/for-v5.5-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull RISC-V fixes from Paul Walmsley: "Three fixes for RISC-V: - Don't free and reuse memory containing the code that CPUs parked at boot reside in. - Fix rv64 build problems for ubsan and some modules by adding logical and arithmetic shift helpers for 128-bit values. These are from libgcc and are similar to what's present for ARM64. - Fix vDSO builds to clean up their own temporary files" * tag 'riscv/for-v5.5-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: riscv: Less inefficient gcc tishift helpers (and export their symbols) riscv: delete temporary files riscv: make sure the cores stay looping in .Lsecondary_park
This commit is contained in:
commit
7008ee1210
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@ -5,4 +5,8 @@
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#include <linux/ftrace.h>
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#include <asm-generic/asm-prototypes.h>
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long long __lshrti3(long long a, int b);
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long long __ashrti3(long long a, int b);
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long long __ashlti3(long long a, int b);
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#endif /* _ASM_RISCV_PROTOTYPES_H */
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@ -80,7 +80,9 @@ _start_kernel:
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#ifdef CONFIG_SMP
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li t0, CONFIG_NR_CPUS
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bgeu a0, t0, .Lsecondary_park
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blt a0, t0, .Lgood_cores
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tail .Lsecondary_park
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.Lgood_cores:
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#endif
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/* Pick one hart to run the main boot sequence */
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@ -209,11 +211,6 @@ relocate:
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tail smp_callin
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#endif
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.align 2
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.Lsecondary_park:
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/* We lack SMP support or have too many harts, so park this hart */
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wfi
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j .Lsecondary_park
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END(_start)
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#ifdef CONFIG_RISCV_M_MODE
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@ -295,6 +292,13 @@ ENTRY(reset_regs)
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END(reset_regs)
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#endif /* CONFIG_RISCV_M_MODE */
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.section ".text", "ax",@progbits
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.align 2
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.Lsecondary_park:
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/* We lack SMP support or have too many harts, so park this hart */
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wfi
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j .Lsecondary_park
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__PAGE_ALIGNED_BSS
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/* Empty zero page */
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.balign PAGE_SIZE
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@ -58,7 +58,8 @@ quiet_cmd_vdsold = VDSOLD $@
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cmd_vdsold = $(CC) $(KBUILD_CFLAGS) $(call cc-option, -no-pie) -nostdlib -nostartfiles $(SYSCFLAGS_$(@F)) \
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-Wl,-T,$(filter-out FORCE,$^) -o $@.tmp && \
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$(CROSS_COMPILE)objcopy \
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$(patsubst %, -G __vdso_%, $(vdso-syms)) $@.tmp $@
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$(patsubst %, -G __vdso_%, $(vdso-syms)) $@.tmp $@ && \
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rm $@.tmp
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# install commands for the unstripped file
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quiet_cmd_vdso_install = INSTALL $@
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@ -4,34 +4,73 @@
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*/
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#include <linux/linkage.h>
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#include <asm-generic/export.h>
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ENTRY(__lshrti3)
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SYM_FUNC_START(__lshrti3)
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beqz a2, .L1
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li a5,64
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sub a5,a5,a2
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addi sp,sp,-16
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sext.w a4,a5
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blez a5, .L2
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sext.w a2,a2
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sll a4,a1,a4
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srl a0,a0,a2
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srl a1,a1,a2
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sll a4,a1,a4
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srl a2,a1,a2
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or a0,a0,a4
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sd a1,8(sp)
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sd a0,0(sp)
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ld a0,0(sp)
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ld a1,8(sp)
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addi sp,sp,16
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ret
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mv a1,a2
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.L1:
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ret
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.L2:
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negw a4,a4
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srl a1,a1,a4
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sd a1,0(sp)
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sd zero,8(sp)
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ld a0,0(sp)
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ld a1,8(sp)
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addi sp,sp,16
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negw a0,a4
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li a2,0
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srl a0,a1,a0
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mv a1,a2
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ret
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ENDPROC(__lshrti3)
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SYM_FUNC_END(__lshrti3)
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EXPORT_SYMBOL(__lshrti3)
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SYM_FUNC_START(__ashrti3)
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beqz a2, .L3
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li a5,64
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sub a5,a5,a2
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sext.w a4,a5
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blez a5, .L4
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sext.w a2,a2
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srl a0,a0,a2
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sll a4,a1,a4
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sra a2,a1,a2
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or a0,a0,a4
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mv a1,a2
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.L3:
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ret
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.L4:
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negw a0,a4
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srai a2,a1,0x3f
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sra a0,a1,a0
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mv a1,a2
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ret
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SYM_FUNC_END(__ashrti3)
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EXPORT_SYMBOL(__ashrti3)
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SYM_FUNC_START(__ashlti3)
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beqz a2, .L5
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li a5,64
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sub a5,a5,a2
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sext.w a4,a5
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blez a5, .L6
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sext.w a2,a2
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sll a1,a1,a2
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srl a4,a0,a4
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sll a2,a0,a2
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or a1,a1,a4
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mv a0,a2
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.L5:
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ret
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.L6:
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negw a1,a4
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li a2,0
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sll a1,a0,a1
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mv a0,a2
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ret
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SYM_FUNC_END(__ashlti3)
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EXPORT_SYMBOL(__ashlti3)
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