bus: ARM CCN PMU driver updates:
- Fixes and improvements for XP watchpoint and events handling - Added missing condition checks for KVM-related exclusions - Improved interrupt affinity handling - Fix for hrtimer use in polling mode - Event grouping implementation improvement -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQEcBAABAgAGBQJXv/z2AAoJEL9jRaJfXa5PDwIIALemTZmwo9rcfS6D2XTZV9PU QhdcJA/rcGhyF0ucmYyEcaObf3Em5V9vF2Zg95H1ZG7g/Dfl2X2UfOs03V8JfhNa b6vbhUg9a/qkNiFbTp3sClWwFJUsOlQY1Ankaw7rv8Ug7YjI1a8PciUanWYLbIdE Zwrw9CSnY1oHzT4XbF+9vVmX21MoDPaHuLqa4KL4tkQwzgRKijDFm7ZZ4pcP5sAV zrORsq7D+SWiFzfH2mPtov68UY7bTHXNZzFX2DhFapqC1ft/x/KYmM1JXvZBrV/q fHYwWXHNJaiHKMGBX+EWSoQGfj+6AGdGE7m6FXq1ITU+I1F/mpQlOqyYOIFvkPM= =1wPT -----END PGP SIGNATURE----- Merge tag 'ccn/fixes-for-4.8-v2' of git://git.linaro.org/people/pawel.moll/linux into fixes Merge "bus: ARM CCN PMU driver updates" from Paweł Moll: - Fixes and improvements for XP watchpoint and events handling - Added missing condition checks for KVM-related exclusions - Improved interrupt affinity handling - Fix for hrtimer use in polling mode - Event grouping implementation improvement * tag 'ccn/fixes-for-4.8-v2' of git://git.linaro.org/people/pawel.moll/linux: bus: arm-ccn: make event groups reliable bus: arm-ccn: fix hrtimer registration bus: arm-ccn: fix PMU interrupt flags bus: arm-ccn: Add missing event attribute exclusions for host/guest bus: arm-ccn: Correct required arguments for XP PMU events bus: arm-ccn: Fix XP watchpoint settings bitmask bus: arm-ccn: Do not attempt to configure XPs for cycle counter bus: arm-ccn: Fix PMU handling of MN
This commit is contained in:
Arnd Bergmann
commit
7064f623c4
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@ -18,13 +18,17 @@ and config2 fields of the perf_event_attr structure. The "events"
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directory provides configuration templates for all documented
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events, that can be used with perf tool. For example "xp_valid_flit"
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is an equivalent of "type=0x8,event=0x4". Other parameters must be
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explicitly specified. For events originating from device, "node"
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defines its index. All crosspoint events require "xp" (index),
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"port" (device port number) and "vc" (virtual channel ID) and
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"dir" (direction). Watchpoints (special "event" value 0xfe) also
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require comparator values ("cmp_l" and "cmp_h") and "mask", being
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index of the comparator mask.
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explicitly specified.
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For events originating from device, "node" defines its index.
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Crosspoint PMU events require "xp" (index), "bus" (bus number)
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and "vc" (virtual channel ID).
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Crosspoint watchpoint-based events (special "event" value 0xfe)
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require "xp" and "vc" as as above plus "port" (device port index),
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"dir" (transmit/receive direction), comparator values ("cmp_l"
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and "cmp_h") and "mask", being index of the comparator mask.
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Masks are defined separately from the event description
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(due to limited number of the config values) in the "cmp_mask"
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directory, with first 8 configurable by user and additional
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@ -187,6 +187,7 @@ struct arm_ccn {
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struct arm_ccn_component *xp;
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struct arm_ccn_dt dt;
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int mn_id;
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};
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static DEFINE_MUTEX(arm_ccn_mutex);
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@ -212,6 +213,7 @@ static int arm_ccn_node_to_xp_port(int node)
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#define CCN_CONFIG_TYPE(_config) (((_config) >> 8) & 0xff)
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#define CCN_CONFIG_EVENT(_config) (((_config) >> 16) & 0xff)
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#define CCN_CONFIG_PORT(_config) (((_config) >> 24) & 0x3)
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#define CCN_CONFIG_BUS(_config) (((_config) >> 24) & 0x3)
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#define CCN_CONFIG_VC(_config) (((_config) >> 26) & 0x7)
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#define CCN_CONFIG_DIR(_config) (((_config) >> 29) & 0x1)
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#define CCN_CONFIG_MASK(_config) (((_config) >> 30) & 0xf)
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@ -241,6 +243,7 @@ static CCN_FORMAT_ATTR(xp, "config:0-7");
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static CCN_FORMAT_ATTR(type, "config:8-15");
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static CCN_FORMAT_ATTR(event, "config:16-23");
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static CCN_FORMAT_ATTR(port, "config:24-25");
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static CCN_FORMAT_ATTR(bus, "config:24-25");
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static CCN_FORMAT_ATTR(vc, "config:26-28");
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static CCN_FORMAT_ATTR(dir, "config:29-29");
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static CCN_FORMAT_ATTR(mask, "config:30-33");
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@ -253,6 +256,7 @@ static struct attribute *arm_ccn_pmu_format_attrs[] = {
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&arm_ccn_pmu_format_attr_type.attr.attr,
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&arm_ccn_pmu_format_attr_event.attr.attr,
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&arm_ccn_pmu_format_attr_port.attr.attr,
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&arm_ccn_pmu_format_attr_bus.attr.attr,
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&arm_ccn_pmu_format_attr_vc.attr.attr,
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&arm_ccn_pmu_format_attr_dir.attr.attr,
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&arm_ccn_pmu_format_attr_mask.attr.attr,
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@ -328,6 +332,7 @@ struct arm_ccn_pmu_event {
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static ssize_t arm_ccn_pmu_event_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev));
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struct arm_ccn_pmu_event *event = container_of(attr,
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struct arm_ccn_pmu_event, attr);
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ssize_t res;
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@ -349,10 +354,17 @@ static ssize_t arm_ccn_pmu_event_show(struct device *dev,
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break;
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case CCN_TYPE_XP:
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res += snprintf(buf + res, PAGE_SIZE - res,
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",xp=?,port=?,vc=?,dir=?");
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",xp=?,vc=?");
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if (event->event == CCN_EVENT_WATCHPOINT)
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res += snprintf(buf + res, PAGE_SIZE - res,
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",cmp_l=?,cmp_h=?,mask=?");
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",port=?,dir=?,cmp_l=?,cmp_h=?,mask=?");
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else
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res += snprintf(buf + res, PAGE_SIZE - res,
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",bus=?");
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break;
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case CCN_TYPE_MN:
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res += snprintf(buf + res, PAGE_SIZE - res, ",node=%d", ccn->mn_id);
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break;
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default:
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res += snprintf(buf + res, PAGE_SIZE - res, ",node=?");
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@ -383,9 +395,9 @@ static umode_t arm_ccn_pmu_events_is_visible(struct kobject *kobj,
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}
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static struct arm_ccn_pmu_event arm_ccn_pmu_events[] = {
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CCN_EVENT_MN(eobarrier, "dir=0,vc=0,cmp_h=0x1c00", CCN_IDX_MASK_OPCODE),
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CCN_EVENT_MN(ecbarrier, "dir=0,vc=0,cmp_h=0x1e00", CCN_IDX_MASK_OPCODE),
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CCN_EVENT_MN(dvmop, "dir=0,vc=0,cmp_h=0x2800", CCN_IDX_MASK_OPCODE),
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CCN_EVENT_MN(eobarrier, "dir=1,vc=0,cmp_h=0x1c00", CCN_IDX_MASK_OPCODE),
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CCN_EVENT_MN(ecbarrier, "dir=1,vc=0,cmp_h=0x1e00", CCN_IDX_MASK_OPCODE),
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CCN_EVENT_MN(dvmop, "dir=1,vc=0,cmp_h=0x2800", CCN_IDX_MASK_OPCODE),
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CCN_EVENT_HNI(txdatflits, "dir=1,vc=3", CCN_IDX_MASK_ANY),
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CCN_EVENT_HNI(rxdatflits, "dir=0,vc=3", CCN_IDX_MASK_ANY),
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CCN_EVENT_HNI(txreqflits, "dir=1,vc=0", CCN_IDX_MASK_ANY),
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@ -733,9 +745,10 @@ static int arm_ccn_pmu_event_init(struct perf_event *event)
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if (has_branch_stack(event) || event->attr.exclude_user ||
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event->attr.exclude_kernel || event->attr.exclude_hv ||
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event->attr.exclude_idle) {
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event->attr.exclude_idle || event->attr.exclude_host ||
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event->attr.exclude_guest) {
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dev_warn(ccn->dev, "Can't exclude execution levels!\n");
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return -EOPNOTSUPP;
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return -EINVAL;
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}
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if (event->cpu < 0) {
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@ -759,6 +772,12 @@ static int arm_ccn_pmu_event_init(struct perf_event *event)
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/* Validate node/xp vs topology */
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switch (type) {
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case CCN_TYPE_MN:
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if (node_xp != ccn->mn_id) {
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dev_warn(ccn->dev, "Invalid MN ID %d!\n", node_xp);
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return -EINVAL;
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}
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break;
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case CCN_TYPE_XP:
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if (node_xp >= ccn->num_xps) {
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dev_warn(ccn->dev, "Invalid XP ID %d!\n", node_xp);
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@ -886,6 +905,10 @@ static void arm_ccn_pmu_xp_dt_config(struct perf_event *event, int enable)
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struct arm_ccn_component *xp;
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u32 val, dt_cfg;
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/* Nothing to do for cycle counter */
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if (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER)
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return;
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if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP)
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xp = &ccn->xp[CCN_CONFIG_XP(event->attr.config)];
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else
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@ -917,38 +940,17 @@ static void arm_ccn_pmu_event_start(struct perf_event *event, int flags)
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arm_ccn_pmu_read_counter(ccn, hw->idx));
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hw->state = 0;
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/*
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* Pin the timer, so that the overflows are handled by the chosen
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* event->cpu (this is the same one as presented in "cpumask"
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* attribute).
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*/
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if (!ccn->irq)
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hrtimer_start(&ccn->dt.hrtimer, arm_ccn_pmu_timer_period(),
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HRTIMER_MODE_REL_PINNED);
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/* Set the DT bus input, engaging the counter */
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arm_ccn_pmu_xp_dt_config(event, 1);
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}
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static void arm_ccn_pmu_event_stop(struct perf_event *event, int flags)
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{
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struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
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struct hw_perf_event *hw = &event->hw;
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u64 timeout;
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/* Disable counting, setting the DT bus to pass-through mode */
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arm_ccn_pmu_xp_dt_config(event, 0);
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if (!ccn->irq)
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hrtimer_cancel(&ccn->dt.hrtimer);
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/* Let the DT bus drain */
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timeout = arm_ccn_pmu_read_counter(ccn, CCN_IDX_PMU_CYCLE_COUNTER) +
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ccn->num_xps;
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while (arm_ccn_pmu_read_counter(ccn, CCN_IDX_PMU_CYCLE_COUNTER) <
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timeout)
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cpu_relax();
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if (flags & PERF_EF_UPDATE)
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arm_ccn_pmu_event_update(event);
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@ -988,7 +990,7 @@ static void arm_ccn_pmu_xp_watchpoint_config(struct perf_event *event)
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/* Comparison values */
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writel(cmp_l & 0xffffffff, source->base + CCN_XP_DT_CMP_VAL_L(wp));
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writel((cmp_l >> 32) & 0xefffffff,
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writel((cmp_l >> 32) & 0x7fffffff,
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source->base + CCN_XP_DT_CMP_VAL_L(wp) + 4);
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writel(cmp_h & 0xffffffff, source->base + CCN_XP_DT_CMP_VAL_H(wp));
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writel((cmp_h >> 32) & 0x0fffffff,
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@ -996,7 +998,7 @@ static void arm_ccn_pmu_xp_watchpoint_config(struct perf_event *event)
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/* Mask */
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writel(mask_l & 0xffffffff, source->base + CCN_XP_DT_CMP_MASK_L(wp));
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writel((mask_l >> 32) & 0xefffffff,
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writel((mask_l >> 32) & 0x7fffffff,
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source->base + CCN_XP_DT_CMP_MASK_L(wp) + 4);
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writel(mask_h & 0xffffffff, source->base + CCN_XP_DT_CMP_MASK_H(wp));
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writel((mask_h >> 32) & 0x0fffffff,
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@ -1014,7 +1016,7 @@ static void arm_ccn_pmu_xp_event_config(struct perf_event *event)
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hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__XP_PMU_EVENT(hw->config_base);
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id = (CCN_CONFIG_VC(event->attr.config) << 4) |
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(CCN_CONFIG_PORT(event->attr.config) << 3) |
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(CCN_CONFIG_BUS(event->attr.config) << 3) |
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(CCN_CONFIG_EVENT(event->attr.config) << 0);
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val = readl(source->base + CCN_XP_PMU_EVENT_SEL);
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@ -1099,15 +1101,31 @@ static void arm_ccn_pmu_event_config(struct perf_event *event)
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spin_unlock(&ccn->dt.config_lock);
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}
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static int arm_ccn_pmu_active_counters(struct arm_ccn *ccn)
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{
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return bitmap_weight(ccn->dt.pmu_counters_mask,
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CCN_NUM_PMU_EVENT_COUNTERS + 1);
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}
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static int arm_ccn_pmu_event_add(struct perf_event *event, int flags)
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{
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int err;
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struct hw_perf_event *hw = &event->hw;
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struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
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err = arm_ccn_pmu_event_alloc(event);
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if (err)
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return err;
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/*
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* Pin the timer, so that the overflows are handled by the chosen
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* event->cpu (this is the same one as presented in "cpumask"
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* attribute).
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*/
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if (!ccn->irq && arm_ccn_pmu_active_counters(ccn) == 1)
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hrtimer_start(&ccn->dt.hrtimer, arm_ccn_pmu_timer_period(),
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HRTIMER_MODE_REL_PINNED);
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arm_ccn_pmu_event_config(event);
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hw->state = PERF_HES_STOPPED;
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@ -1120,9 +1138,14 @@ static int arm_ccn_pmu_event_add(struct perf_event *event, int flags)
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static void arm_ccn_pmu_event_del(struct perf_event *event, int flags)
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{
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struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
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arm_ccn_pmu_event_stop(event, PERF_EF_UPDATE);
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arm_ccn_pmu_event_release(event);
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if (!ccn->irq && arm_ccn_pmu_active_counters(ccn) == 0)
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hrtimer_cancel(&ccn->dt.hrtimer);
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}
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static void arm_ccn_pmu_event_read(struct perf_event *event)
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@ -1130,6 +1153,24 @@ static void arm_ccn_pmu_event_read(struct perf_event *event)
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arm_ccn_pmu_event_update(event);
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}
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static void arm_ccn_pmu_enable(struct pmu *pmu)
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{
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struct arm_ccn *ccn = pmu_to_arm_ccn(pmu);
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u32 val = readl(ccn->dt.base + CCN_DT_PMCR);
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val |= CCN_DT_PMCR__PMU_EN;
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writel(val, ccn->dt.base + CCN_DT_PMCR);
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}
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static void arm_ccn_pmu_disable(struct pmu *pmu)
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{
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struct arm_ccn *ccn = pmu_to_arm_ccn(pmu);
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u32 val = readl(ccn->dt.base + CCN_DT_PMCR);
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val &= ~CCN_DT_PMCR__PMU_EN;
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writel(val, ccn->dt.base + CCN_DT_PMCR);
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}
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static irqreturn_t arm_ccn_pmu_overflow_handler(struct arm_ccn_dt *dt)
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{
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u32 pmovsr = readl(dt->base + CCN_DT_PMOVSR);
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@ -1252,6 +1293,8 @@ static int arm_ccn_pmu_init(struct arm_ccn *ccn)
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.start = arm_ccn_pmu_event_start,
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.stop = arm_ccn_pmu_event_stop,
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.read = arm_ccn_pmu_event_read,
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.pmu_enable = arm_ccn_pmu_enable,
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.pmu_disable = arm_ccn_pmu_disable,
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};
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/* No overflow interrupt? Have to use a timer instead. */
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@ -1361,6 +1404,8 @@ static int arm_ccn_init_nodes(struct arm_ccn *ccn, int region,
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switch (type) {
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case CCN_TYPE_MN:
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ccn->mn_id = id;
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return 0;
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case CCN_TYPE_DT:
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return 0;
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case CCN_TYPE_XP:
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@ -1471,8 +1516,9 @@ static int arm_ccn_probe(struct platform_device *pdev)
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/* Can set 'disable' bits, so can acknowledge interrupts */
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writel(CCN_MN_ERRINT_STATUS__PMU_EVENTS__ENABLE,
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ccn->base + CCN_MN_ERRINT_STATUS);
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err = devm_request_irq(ccn->dev, irq, arm_ccn_irq_handler, 0,
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dev_name(ccn->dev), ccn);
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err = devm_request_irq(ccn->dev, irq, arm_ccn_irq_handler,
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IRQF_NOBALANCING | IRQF_NO_THREAD,
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dev_name(ccn->dev), ccn);
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if (err)
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return err;
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