powerpc: Convert fsl_rstcr_restart to a reset handler
Convert fsl_rstcr_restart into a function to be registered with register_reset_handler(). Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> [scottwood: Converted mvme7100 as well] Signed-off-by: Scott Wood <oss@buserror.net>
This commit is contained in:
parent
ad24747304
commit
7120438e5d
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@ -72,7 +72,6 @@ define_machine(bsc9132_qds) {
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.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
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.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
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#endif
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#endif
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.get_irq = mpic_get_irq,
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.get_irq = mpic_get_irq,
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.restart = fsl_rstcr_restart,
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.calibrate_decr = generic_calibrate_decr,
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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.progress = udbg_progress,
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};
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};
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@ -59,7 +59,6 @@ define_machine(bsc9131_rdb) {
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.setup_arch = bsc913x_rdb_setup_arch,
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.setup_arch = bsc913x_rdb_setup_arch,
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.init_IRQ = bsc913x_rdb_pic_init,
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.init_IRQ = bsc913x_rdb_pic_init,
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.get_irq = mpic_get_irq,
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.get_irq = mpic_get_irq,
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.restart = fsl_rstcr_restart,
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.calibrate_decr = generic_calibrate_decr,
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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.progress = udbg_progress,
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};
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};
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@ -65,7 +65,6 @@ define_machine(c293_pcie) {
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.setup_arch = c293_pcie_setup_arch,
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.setup_arch = c293_pcie_setup_arch,
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.init_IRQ = c293_pcie_pic_init,
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.init_IRQ = c293_pcie_pic_init,
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.get_irq = mpic_get_irq,
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.get_irq = mpic_get_irq,
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.restart = fsl_rstcr_restart,
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.calibrate_decr = generic_calibrate_decr,
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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.progress = udbg_progress,
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};
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};
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@ -225,7 +225,6 @@ define_machine(corenet_generic) {
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#else
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#else
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.get_irq = mpic_get_coreint_irq,
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.get_irq = mpic_get_coreint_irq,
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#endif
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#endif
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.restart = fsl_rstcr_restart,
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.calibrate_decr = generic_calibrate_decr,
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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.progress = udbg_progress,
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#ifdef CONFIG_PPC64
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#ifdef CONFIG_PPC64
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@ -215,7 +215,6 @@ define_machine(ge_imp3a) {
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.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
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.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
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#endif
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#endif
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.get_irq = mpic_get_irq,
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.get_irq = mpic_get_irq,
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.restart = fsl_rstcr_restart,
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.calibrate_decr = generic_calibrate_decr,
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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.progress = udbg_progress,
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};
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};
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@ -77,7 +77,6 @@ define_machine(mpc8536_ds) {
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.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
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.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
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#endif
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#endif
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.get_irq = mpic_get_irq,
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.get_irq = mpic_get_irq,
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.restart = fsl_rstcr_restart,
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.calibrate_decr = generic_calibrate_decr,
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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.progress = udbg_progress,
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};
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};
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@ -170,7 +170,6 @@ define_machine(mpc85xx_ads) {
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.init_IRQ = mpc85xx_ads_pic_init,
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.init_IRQ = mpc85xx_ads_pic_init,
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.show_cpuinfo = mpc85xx_ads_show_cpuinfo,
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.show_cpuinfo = mpc85xx_ads_show_cpuinfo,
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.get_irq = mpic_get_irq,
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.get_irq = mpic_get_irq,
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.restart = fsl_rstcr_restart,
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.calibrate_decr = generic_calibrate_decr,
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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.progress = udbg_progress,
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};
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};
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@ -83,7 +83,8 @@ static int mpc85xx_exclude_device(struct pci_controller *hose,
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return PCIBIOS_SUCCESSFUL;
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return PCIBIOS_SUCCESSFUL;
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}
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}
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static void __noreturn mpc85xx_cds_restart(char *cmd)
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static int mpc85xx_cds_restart(struct notifier_block *this,
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unsigned long mode, void *cmd)
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{
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{
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struct pci_dev *dev;
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struct pci_dev *dev;
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u_char tmp;
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u_char tmp;
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@ -108,12 +109,25 @@ static void __noreturn mpc85xx_cds_restart(char *cmd)
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}
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}
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/*
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/*
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* If we can't find the VIA chip (maybe the P2P bridge is disabled)
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* If we can't find the VIA chip (maybe the P2P bridge is
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* or the VIA chip reset didn't work, just use the default reset.
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* disabled) or the VIA chip reset didn't work, just return
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* and let default reset sequence happen.
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*/
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*/
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fsl_rstcr_restart(NULL);
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return NOTIFY_DONE;
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}
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}
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static int mpc85xx_cds_restart_register(void)
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{
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static struct notifier_block restart_handler;
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restart_handler.notifier_call = mpc85xx_cds_restart;
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restart_handler.priority = 192;
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return register_restart_handler(&restart_handler);
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}
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machine_arch_initcall(mpc85xx_cds, mpc85xx_cds_restart_register);
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static void __init mpc85xx_cds_pci_irq_fixup(struct pci_dev *dev)
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static void __init mpc85xx_cds_pci_irq_fixup(struct pci_dev *dev)
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{
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{
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u_char c;
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u_char c;
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@ -380,11 +394,8 @@ define_machine(mpc85xx_cds) {
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.show_cpuinfo = mpc85xx_cds_show_cpuinfo,
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.show_cpuinfo = mpc85xx_cds_show_cpuinfo,
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.get_irq = mpic_get_irq,
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.get_irq = mpic_get_irq,
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#ifdef CONFIG_PCI
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#ifdef CONFIG_PCI
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.restart = mpc85xx_cds_restart,
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.pcibios_fixup_bus = mpc85xx_cds_fixup_bus,
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.pcibios_fixup_bus = mpc85xx_cds_fixup_bus,
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.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
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.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
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#else
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.restart = fsl_rstcr_restart,
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#endif
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#endif
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.calibrate_decr = generic_calibrate_decr,
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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.progress = udbg_progress,
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@ -204,7 +204,6 @@ define_machine(mpc8544_ds) {
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.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
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.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
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#endif
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#endif
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.get_irq = mpic_get_irq,
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.get_irq = mpic_get_irq,
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.restart = fsl_rstcr_restart,
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.calibrate_decr = generic_calibrate_decr,
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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.progress = udbg_progress,
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};
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};
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@ -219,7 +218,6 @@ define_machine(mpc8572_ds) {
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.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
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.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
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#endif
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#endif
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.get_irq = mpic_get_irq,
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.get_irq = mpic_get_irq,
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.restart = fsl_rstcr_restart,
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.calibrate_decr = generic_calibrate_decr,
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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.progress = udbg_progress,
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};
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};
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@ -234,7 +232,6 @@ define_machine(p2020_ds) {
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.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
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.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
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#endif
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#endif
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.get_irq = mpic_get_irq,
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.get_irq = mpic_get_irq,
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.restart = fsl_rstcr_restart,
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.calibrate_decr = generic_calibrate_decr,
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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.progress = udbg_progress,
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};
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};
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@ -393,7 +393,6 @@ define_machine(mpc8568_mds) {
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.setup_arch = mpc85xx_mds_setup_arch,
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.setup_arch = mpc85xx_mds_setup_arch,
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.init_IRQ = mpc85xx_mds_pic_init,
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.init_IRQ = mpc85xx_mds_pic_init,
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.get_irq = mpic_get_irq,
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.get_irq = mpic_get_irq,
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.restart = fsl_rstcr_restart,
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.calibrate_decr = generic_calibrate_decr,
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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.progress = udbg_progress,
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#ifdef CONFIG_PCI
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#ifdef CONFIG_PCI
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@ -413,7 +412,6 @@ define_machine(mpc8569_mds) {
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.setup_arch = mpc85xx_mds_setup_arch,
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.setup_arch = mpc85xx_mds_setup_arch,
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.init_IRQ = mpc85xx_mds_pic_init,
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.init_IRQ = mpc85xx_mds_pic_init,
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.get_irq = mpic_get_irq,
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.get_irq = mpic_get_irq,
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.restart = fsl_rstcr_restart,
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.calibrate_decr = generic_calibrate_decr,
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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.progress = udbg_progress,
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#ifdef CONFIG_PCI
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#ifdef CONFIG_PCI
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@ -434,7 +432,6 @@ define_machine(p1021_mds) {
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.setup_arch = mpc85xx_mds_setup_arch,
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.setup_arch = mpc85xx_mds_setup_arch,
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.init_IRQ = mpc85xx_mds_pic_init,
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.init_IRQ = mpc85xx_mds_pic_init,
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.get_irq = mpic_get_irq,
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.get_irq = mpic_get_irq,
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.restart = fsl_rstcr_restart,
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.calibrate_decr = generic_calibrate_decr,
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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.progress = udbg_progress,
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#ifdef CONFIG_PCI
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#ifdef CONFIG_PCI
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@ -213,7 +213,6 @@ define_machine(p2020_rdb) {
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.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
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.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
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#endif
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#endif
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.get_irq = mpic_get_irq,
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.get_irq = mpic_get_irq,
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.restart = fsl_rstcr_restart,
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.calibrate_decr = generic_calibrate_decr,
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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.progress = udbg_progress,
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};
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};
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@ -228,7 +227,6 @@ define_machine(p1020_rdb) {
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.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
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.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
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#endif
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#endif
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.get_irq = mpic_get_irq,
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.get_irq = mpic_get_irq,
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.restart = fsl_rstcr_restart,
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.calibrate_decr = generic_calibrate_decr,
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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.progress = udbg_progress,
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};
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};
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@ -243,7 +241,6 @@ define_machine(p1021_rdb_pc) {
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.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
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.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
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#endif
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#endif
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.get_irq = mpic_get_irq,
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.get_irq = mpic_get_irq,
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.restart = fsl_rstcr_restart,
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.calibrate_decr = generic_calibrate_decr,
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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.progress = udbg_progress,
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};
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};
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@ -258,7 +255,6 @@ define_machine(p2020_rdb_pc) {
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.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
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.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
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#endif
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#endif
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.get_irq = mpic_get_irq,
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.get_irq = mpic_get_irq,
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.restart = fsl_rstcr_restart,
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.calibrate_decr = generic_calibrate_decr,
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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.progress = udbg_progress,
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};
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};
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@ -273,7 +269,6 @@ define_machine(p1025_rdb) {
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.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
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.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
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#endif
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#endif
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.get_irq = mpic_get_irq,
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.get_irq = mpic_get_irq,
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.restart = fsl_rstcr_restart,
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.calibrate_decr = generic_calibrate_decr,
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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.progress = udbg_progress,
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};
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};
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@ -288,7 +283,6 @@ define_machine(p1020_mbg_pc) {
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.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
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.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
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#endif
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#endif
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.get_irq = mpic_get_irq,
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.get_irq = mpic_get_irq,
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.restart = fsl_rstcr_restart,
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.calibrate_decr = generic_calibrate_decr,
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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.progress = udbg_progress,
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};
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};
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@ -303,7 +297,6 @@ define_machine(p1020_utm_pc) {
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.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
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.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
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#endif
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#endif
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.get_irq = mpic_get_irq,
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.get_irq = mpic_get_irq,
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.restart = fsl_rstcr_restart,
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.calibrate_decr = generic_calibrate_decr,
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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.progress = udbg_progress,
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};
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};
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@ -318,7 +311,6 @@ define_machine(p1020_rdb_pc) {
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.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
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.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
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#endif
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#endif
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.get_irq = mpic_get_irq,
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.get_irq = mpic_get_irq,
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.restart = fsl_rstcr_restart,
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.calibrate_decr = generic_calibrate_decr,
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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.progress = udbg_progress,
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};
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};
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@ -333,7 +325,6 @@ define_machine(p1020_rdb_pd) {
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.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
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.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
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#endif
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#endif
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.get_irq = mpic_get_irq,
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.get_irq = mpic_get_irq,
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.restart = fsl_rstcr_restart,
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.calibrate_decr = generic_calibrate_decr,
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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.progress = udbg_progress,
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};
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};
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@ -348,7 +339,6 @@ define_machine(p1024_rdb) {
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.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
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.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
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#endif
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#endif
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.get_irq = mpic_get_irq,
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.get_irq = mpic_get_irq,
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.restart = fsl_rstcr_restart,
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.calibrate_decr = generic_calibrate_decr,
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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.progress = udbg_progress,
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};
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};
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@ -66,7 +66,6 @@ define_machine(mvme2500) {
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.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
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.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
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#endif
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#endif
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.get_irq = mpic_get_irq,
|
.get_irq = mpic_get_irq,
|
||||||
.restart = fsl_rstcr_restart,
|
|
||||||
.calibrate_decr = generic_calibrate_decr,
|
.calibrate_decr = generic_calibrate_decr,
|
||||||
.progress = udbg_progress,
|
.progress = udbg_progress,
|
||||||
};
|
};
|
||||||
|
|
|
@ -79,7 +79,6 @@ define_machine(p1010_rdb) {
|
||||||
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
|
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
|
||||||
#endif
|
#endif
|
||||||
.get_irq = mpic_get_irq,
|
.get_irq = mpic_get_irq,
|
||||||
.restart = fsl_rstcr_restart,
|
|
||||||
.calibrate_decr = generic_calibrate_decr,
|
.calibrate_decr = generic_calibrate_decr,
|
||||||
.progress = udbg_progress,
|
.progress = udbg_progress,
|
||||||
};
|
};
|
||||||
|
|
|
@ -568,7 +568,6 @@ define_machine(p1022_ds) {
|
||||||
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
|
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
|
||||||
#endif
|
#endif
|
||||||
.get_irq = mpic_get_irq,
|
.get_irq = mpic_get_irq,
|
||||||
.restart = fsl_rstcr_restart,
|
|
||||||
.calibrate_decr = generic_calibrate_decr,
|
.calibrate_decr = generic_calibrate_decr,
|
||||||
.progress = udbg_progress,
|
.progress = udbg_progress,
|
||||||
};
|
};
|
||||||
|
|
|
@ -148,7 +148,6 @@ define_machine(p1022_rdk) {
|
||||||
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
|
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
|
||||||
#endif
|
#endif
|
||||||
.get_irq = mpic_get_irq,
|
.get_irq = mpic_get_irq,
|
||||||
.restart = fsl_rstcr_restart,
|
|
||||||
.calibrate_decr = generic_calibrate_decr,
|
.calibrate_decr = generic_calibrate_decr,
|
||||||
.progress = udbg_progress,
|
.progress = udbg_progress,
|
||||||
};
|
};
|
||||||
|
|
|
@ -110,7 +110,6 @@ define_machine(p1023_rdb) {
|
||||||
.setup_arch = mpc85xx_rdb_setup_arch,
|
.setup_arch = mpc85xx_rdb_setup_arch,
|
||||||
.init_IRQ = mpc85xx_rdb_pic_init,
|
.init_IRQ = mpc85xx_rdb_pic_init,
|
||||||
.get_irq = mpic_get_irq,
|
.get_irq = mpic_get_irq,
|
||||||
.restart = fsl_rstcr_restart,
|
|
||||||
.calibrate_decr = generic_calibrate_decr,
|
.calibrate_decr = generic_calibrate_decr,
|
||||||
.progress = udbg_progress,
|
.progress = udbg_progress,
|
||||||
#ifdef CONFIG_PCI
|
#ifdef CONFIG_PCI
|
||||||
|
|
|
@ -91,7 +91,6 @@ define_machine(ppa8548) {
|
||||||
.init_IRQ = ppa8548_pic_init,
|
.init_IRQ = ppa8548_pic_init,
|
||||||
.show_cpuinfo = ppa8548_show_cpuinfo,
|
.show_cpuinfo = ppa8548_show_cpuinfo,
|
||||||
.get_irq = mpic_get_irq,
|
.get_irq = mpic_get_irq,
|
||||||
.restart = fsl_rstcr_restart,
|
|
||||||
.calibrate_decr = generic_calibrate_decr,
|
.calibrate_decr = generic_calibrate_decr,
|
||||||
.progress = udbg_progress,
|
.progress = udbg_progress,
|
||||||
};
|
};
|
||||||
|
|
|
@ -77,7 +77,6 @@ define_machine(qemu_e500) {
|
||||||
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
|
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
|
||||||
#endif
|
#endif
|
||||||
.get_irq = mpic_get_coreint_irq,
|
.get_irq = mpic_get_coreint_irq,
|
||||||
.restart = fsl_rstcr_restart,
|
|
||||||
.calibrate_decr = generic_calibrate_decr,
|
.calibrate_decr = generic_calibrate_decr,
|
||||||
.progress = udbg_progress,
|
.progress = udbg_progress,
|
||||||
};
|
};
|
||||||
|
|
|
@ -130,7 +130,6 @@ define_machine(sbc8548) {
|
||||||
.init_IRQ = sbc8548_pic_init,
|
.init_IRQ = sbc8548_pic_init,
|
||||||
.show_cpuinfo = sbc8548_show_cpuinfo,
|
.show_cpuinfo = sbc8548_show_cpuinfo,
|
||||||
.get_irq = mpic_get_irq,
|
.get_irq = mpic_get_irq,
|
||||||
.restart = fsl_rstcr_restart,
|
|
||||||
#ifdef CONFIG_PCI
|
#ifdef CONFIG_PCI
|
||||||
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
|
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
|
||||||
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
|
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
|
||||||
|
|
|
@ -91,7 +91,6 @@ define_machine(socrates) {
|
||||||
.setup_arch = socrates_setup_arch,
|
.setup_arch = socrates_setup_arch,
|
||||||
.init_IRQ = socrates_pic_init,
|
.init_IRQ = socrates_pic_init,
|
||||||
.get_irq = mpic_get_irq,
|
.get_irq = mpic_get_irq,
|
||||||
.restart = fsl_rstcr_restart,
|
|
||||||
.calibrate_decr = generic_calibrate_decr,
|
.calibrate_decr = generic_calibrate_decr,
|
||||||
.progress = udbg_progress,
|
.progress = udbg_progress,
|
||||||
};
|
};
|
||||||
|
|
|
@ -103,7 +103,6 @@ define_machine(stx_gp3) {
|
||||||
.init_IRQ = stx_gp3_pic_init,
|
.init_IRQ = stx_gp3_pic_init,
|
||||||
.show_cpuinfo = stx_gp3_show_cpuinfo,
|
.show_cpuinfo = stx_gp3_show_cpuinfo,
|
||||||
.get_irq = mpic_get_irq,
|
.get_irq = mpic_get_irq,
|
||||||
.restart = fsl_rstcr_restart,
|
|
||||||
.calibrate_decr = generic_calibrate_decr,
|
.calibrate_decr = generic_calibrate_decr,
|
||||||
.progress = udbg_progress,
|
.progress = udbg_progress,
|
||||||
};
|
};
|
||||||
|
|
|
@ -132,7 +132,6 @@ define_machine(tqm85xx) {
|
||||||
.init_IRQ = tqm85xx_pic_init,
|
.init_IRQ = tqm85xx_pic_init,
|
||||||
.show_cpuinfo = tqm85xx_show_cpuinfo,
|
.show_cpuinfo = tqm85xx_show_cpuinfo,
|
||||||
.get_irq = mpic_get_irq,
|
.get_irq = mpic_get_irq,
|
||||||
.restart = fsl_rstcr_restart,
|
|
||||||
.calibrate_decr = generic_calibrate_decr,
|
.calibrate_decr = generic_calibrate_decr,
|
||||||
.progress = udbg_progress,
|
.progress = udbg_progress,
|
||||||
};
|
};
|
||||||
|
|
|
@ -140,7 +140,6 @@ define_machine(twr_p1025) {
|
||||||
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
|
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
|
||||||
#endif
|
#endif
|
||||||
.get_irq = mpic_get_irq,
|
.get_irq = mpic_get_irq,
|
||||||
.restart = fsl_rstcr_restart,
|
|
||||||
.calibrate_decr = generic_calibrate_decr,
|
.calibrate_decr = generic_calibrate_decr,
|
||||||
.progress = udbg_progress,
|
.progress = udbg_progress,
|
||||||
};
|
};
|
||||||
|
|
|
@ -167,7 +167,6 @@ define_machine(xes_mpc8572) {
|
||||||
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
|
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
|
||||||
#endif
|
#endif
|
||||||
.get_irq = mpic_get_irq,
|
.get_irq = mpic_get_irq,
|
||||||
.restart = fsl_rstcr_restart,
|
|
||||||
.calibrate_decr = generic_calibrate_decr,
|
.calibrate_decr = generic_calibrate_decr,
|
||||||
.progress = udbg_progress,
|
.progress = udbg_progress,
|
||||||
};
|
};
|
||||||
|
@ -182,7 +181,6 @@ define_machine(xes_mpc8548) {
|
||||||
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
|
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
|
||||||
#endif
|
#endif
|
||||||
.get_irq = mpic_get_irq,
|
.get_irq = mpic_get_irq,
|
||||||
.restart = fsl_rstcr_restart,
|
|
||||||
.calibrate_decr = generic_calibrate_decr,
|
.calibrate_decr = generic_calibrate_decr,
|
||||||
.progress = udbg_progress,
|
.progress = udbg_progress,
|
||||||
};
|
};
|
||||||
|
@ -197,7 +195,6 @@ define_machine(xes_mpc8540) {
|
||||||
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
|
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
|
||||||
#endif
|
#endif
|
||||||
.get_irq = mpic_get_irq,
|
.get_irq = mpic_get_irq,
|
||||||
.restart = fsl_rstcr_restart,
|
|
||||||
.calibrate_decr = generic_calibrate_decr,
|
.calibrate_decr = generic_calibrate_decr,
|
||||||
.progress = udbg_progress,
|
.progress = udbg_progress,
|
||||||
};
|
};
|
||||||
|
|
|
@ -204,7 +204,6 @@ define_machine(gef_ppc9a) {
|
||||||
.init_IRQ = gef_ppc9a_init_irq,
|
.init_IRQ = gef_ppc9a_init_irq,
|
||||||
.show_cpuinfo = gef_ppc9a_show_cpuinfo,
|
.show_cpuinfo = gef_ppc9a_show_cpuinfo,
|
||||||
.get_irq = mpic_get_irq,
|
.get_irq = mpic_get_irq,
|
||||||
.restart = fsl_rstcr_restart,
|
|
||||||
.time_init = mpc86xx_time_init,
|
.time_init = mpc86xx_time_init,
|
||||||
.calibrate_decr = generic_calibrate_decr,
|
.calibrate_decr = generic_calibrate_decr,
|
||||||
.progress = udbg_progress,
|
.progress = udbg_progress,
|
||||||
|
|
|
@ -191,7 +191,6 @@ define_machine(gef_sbc310) {
|
||||||
.init_IRQ = gef_sbc310_init_irq,
|
.init_IRQ = gef_sbc310_init_irq,
|
||||||
.show_cpuinfo = gef_sbc310_show_cpuinfo,
|
.show_cpuinfo = gef_sbc310_show_cpuinfo,
|
||||||
.get_irq = mpic_get_irq,
|
.get_irq = mpic_get_irq,
|
||||||
.restart = fsl_rstcr_restart,
|
|
||||||
.time_init = mpc86xx_time_init,
|
.time_init = mpc86xx_time_init,
|
||||||
.calibrate_decr = generic_calibrate_decr,
|
.calibrate_decr = generic_calibrate_decr,
|
||||||
.progress = udbg_progress,
|
.progress = udbg_progress,
|
||||||
|
|
|
@ -181,7 +181,6 @@ define_machine(gef_sbc610) {
|
||||||
.init_IRQ = gef_sbc610_init_irq,
|
.init_IRQ = gef_sbc610_init_irq,
|
||||||
.show_cpuinfo = gef_sbc610_show_cpuinfo,
|
.show_cpuinfo = gef_sbc610_show_cpuinfo,
|
||||||
.get_irq = mpic_get_irq,
|
.get_irq = mpic_get_irq,
|
||||||
.restart = fsl_rstcr_restart,
|
|
||||||
.time_init = mpc86xx_time_init,
|
.time_init = mpc86xx_time_init,
|
||||||
.calibrate_decr = generic_calibrate_decr,
|
.calibrate_decr = generic_calibrate_decr,
|
||||||
.progress = udbg_progress,
|
.progress = udbg_progress,
|
||||||
|
|
|
@ -331,7 +331,6 @@ define_machine(mpc86xx_hpcd) {
|
||||||
.setup_arch = mpc86xx_hpcd_setup_arch,
|
.setup_arch = mpc86xx_hpcd_setup_arch,
|
||||||
.init_IRQ = mpc86xx_init_irq,
|
.init_IRQ = mpc86xx_init_irq,
|
||||||
.get_irq = mpic_get_irq,
|
.get_irq = mpic_get_irq,
|
||||||
.restart = fsl_rstcr_restart,
|
|
||||||
.time_init = mpc86xx_time_init,
|
.time_init = mpc86xx_time_init,
|
||||||
.calibrate_decr = generic_calibrate_decr,
|
.calibrate_decr = generic_calibrate_decr,
|
||||||
.progress = udbg_progress,
|
.progress = udbg_progress,
|
||||||
|
|
|
@ -130,7 +130,6 @@ define_machine(mpc86xx_hpcn) {
|
||||||
.init_IRQ = mpc86xx_init_irq,
|
.init_IRQ = mpc86xx_init_irq,
|
||||||
.show_cpuinfo = mpc86xx_hpcn_show_cpuinfo,
|
.show_cpuinfo = mpc86xx_hpcn_show_cpuinfo,
|
||||||
.get_irq = mpic_get_irq,
|
.get_irq = mpic_get_irq,
|
||||||
.restart = fsl_rstcr_restart,
|
|
||||||
.time_init = mpc86xx_time_init,
|
.time_init = mpc86xx_time_init,
|
||||||
.calibrate_decr = generic_calibrate_decr,
|
.calibrate_decr = generic_calibrate_decr,
|
||||||
.progress = udbg_progress,
|
.progress = udbg_progress,
|
||||||
|
|
|
@ -111,7 +111,6 @@ define_machine(mvme7100) {
|
||||||
.setup_arch = mvme7100_setup_arch,
|
.setup_arch = mvme7100_setup_arch,
|
||||||
.init_IRQ = mpc86xx_init_irq,
|
.init_IRQ = mpc86xx_init_irq,
|
||||||
.get_irq = mpic_get_irq,
|
.get_irq = mpic_get_irq,
|
||||||
.restart = fsl_rstcr_restart,
|
|
||||||
.time_init = mpc86xx_time_init,
|
.time_init = mpc86xx_time_init,
|
||||||
.calibrate_decr = generic_calibrate_decr,
|
.calibrate_decr = generic_calibrate_decr,
|
||||||
.progress = udbg_progress,
|
.progress = udbg_progress,
|
||||||
|
|
|
@ -82,7 +82,6 @@ define_machine(sbc8641) {
|
||||||
.init_IRQ = mpc86xx_init_irq,
|
.init_IRQ = mpc86xx_init_irq,
|
||||||
.show_cpuinfo = sbc8641_show_cpuinfo,
|
.show_cpuinfo = sbc8641_show_cpuinfo,
|
||||||
.get_irq = mpic_get_irq,
|
.get_irq = mpic_get_irq,
|
||||||
.restart = fsl_rstcr_restart,
|
|
||||||
.time_init = mpc86xx_time_init,
|
.time_init = mpc86xx_time_init,
|
||||||
.calibrate_decr = generic_calibrate_decr,
|
.calibrate_decr = generic_calibrate_decr,
|
||||||
.progress = udbg_progress,
|
.progress = udbg_progress,
|
||||||
|
|
|
@ -29,6 +29,7 @@
|
||||||
#include <linux/fsl_devices.h>
|
#include <linux/fsl_devices.h>
|
||||||
#include <linux/fs_enet_pd.h>
|
#include <linux/fs_enet_pd.h>
|
||||||
#include <linux/fs_uart_pd.h>
|
#include <linux/fs_uart_pd.h>
|
||||||
|
#include <linux/reboot.h>
|
||||||
|
|
||||||
#include <linux/atomic.h>
|
#include <linux/atomic.h>
|
||||||
#include <asm/io.h>
|
#include <asm/io.h>
|
||||||
|
@ -180,23 +181,38 @@ EXPORT_SYMBOL(get_baudrate);
|
||||||
#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
|
#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
|
||||||
static __be32 __iomem *rstcr;
|
static __be32 __iomem *rstcr;
|
||||||
|
|
||||||
|
static int fsl_rstcr_restart(struct notifier_block *this,
|
||||||
|
unsigned long mode, void *cmd)
|
||||||
|
{
|
||||||
|
local_irq_disable();
|
||||||
|
/* set reset control register */
|
||||||
|
out_be32(rstcr, 0x2); /* HRESET_REQ */
|
||||||
|
|
||||||
|
return NOTIFY_DONE;
|
||||||
|
}
|
||||||
|
|
||||||
static int __init setup_rstcr(void)
|
static int __init setup_rstcr(void)
|
||||||
{
|
{
|
||||||
struct device_node *np;
|
struct device_node *np;
|
||||||
|
|
||||||
|
static struct notifier_block restart_handler = {
|
||||||
|
.notifier_call = fsl_rstcr_restart,
|
||||||
|
.priority = 128,
|
||||||
|
};
|
||||||
|
|
||||||
for_each_node_by_name(np, "global-utilities") {
|
for_each_node_by_name(np, "global-utilities") {
|
||||||
if ((of_get_property(np, "fsl,has-rstcr", NULL))) {
|
if ((of_get_property(np, "fsl,has-rstcr", NULL))) {
|
||||||
rstcr = of_iomap(np, 0) + 0xb0;
|
rstcr = of_iomap(np, 0) + 0xb0;
|
||||||
if (!rstcr)
|
if (!rstcr) {
|
||||||
printk (KERN_ERR "Error: reset control "
|
printk (KERN_ERR "Error: reset control "
|
||||||
"register not mapped!\n");
|
"register not mapped!\n");
|
||||||
|
} else {
|
||||||
|
register_restart_handler(&restart_handler);
|
||||||
|
}
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
if (!rstcr && ppc_md.restart == fsl_rstcr_restart)
|
|
||||||
printk(KERN_ERR "No RSTCR register, warm reboot won't work\n");
|
|
||||||
|
|
||||||
of_node_put(np);
|
of_node_put(np);
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
|
@ -204,15 +220,6 @@ static int __init setup_rstcr(void)
|
||||||
|
|
||||||
arch_initcall(setup_rstcr);
|
arch_initcall(setup_rstcr);
|
||||||
|
|
||||||
void __noreturn fsl_rstcr_restart(char *cmd)
|
|
||||||
{
|
|
||||||
local_irq_disable();
|
|
||||||
if (rstcr)
|
|
||||||
/* set reset control register */
|
|
||||||
out_be32(rstcr, 0x2); /* HRESET_REQ */
|
|
||||||
|
|
||||||
while (1) ;
|
|
||||||
}
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
|
#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
|
||||||
|
|
|
@ -19,8 +19,6 @@ extern u32 fsl_get_sys_freq(void);
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struct spi_board_info;
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struct spi_board_info;
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struct device_node;
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struct device_node;
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extern void __noreturn fsl_rstcr_restart(char *cmd);
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/* The different ports that the DIU can be connected to */
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/* The different ports that the DIU can be connected to */
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enum fsl_diu_monitor_port {
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enum fsl_diu_monitor_port {
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FSL_DIU_PORT_DVI, /* DVI */
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FSL_DIU_PORT_DVI, /* DVI */
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||||||
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Reference in New Issue