drm/amdgpu: consolidate atom scratch reg handling for hangs
Move from asic specific code to common atom code. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1784,6 +1784,19 @@ void amdgpu_atombios_scratch_regs_restore(struct amdgpu_device *adev)
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WREG32(mmBIOS_SCRATCH_0 + i, adev->bios_scratch[i]);
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WREG32(mmBIOS_SCRATCH_0 + i, adev->bios_scratch[i]);
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}
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}
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void amdgpu_atombios_scratch_regs_engine_hung(struct amdgpu_device *adev,
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bool hung)
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{
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u32 tmp = RREG32(mmBIOS_SCRATCH_3);
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if (hung)
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tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG;
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else
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tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG;
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WREG32(mmBIOS_SCRATCH_3, tmp);
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}
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/* Atom needs data in little endian format
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/* Atom needs data in little endian format
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* so swap as appropriate when copying data to
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* so swap as appropriate when copying data to
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* or from atom. Note that atom operates on
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* or from atom. Note that atom operates on
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@ -206,6 +206,8 @@ void amdgpu_atombios_scratch_regs_lock(struct amdgpu_device *adev, bool lock);
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void amdgpu_atombios_scratch_regs_init(struct amdgpu_device *adev);
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void amdgpu_atombios_scratch_regs_init(struct amdgpu_device *adev);
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void amdgpu_atombios_scratch_regs_save(struct amdgpu_device *adev);
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void amdgpu_atombios_scratch_regs_save(struct amdgpu_device *adev);
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void amdgpu_atombios_scratch_regs_restore(struct amdgpu_device *adev);
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void amdgpu_atombios_scratch_regs_restore(struct amdgpu_device *adev);
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void amdgpu_atombios_scratch_regs_engine_hung(struct amdgpu_device *adev,
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bool hung);
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void amdgpu_atombios_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le);
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void amdgpu_atombios_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le);
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int amdgpu_atombios_get_max_vddc(struct amdgpu_device *adev, u8 voltage_type,
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int amdgpu_atombios_get_max_vddc(struct amdgpu_device *adev, u8 voltage_type,
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@ -1189,18 +1189,6 @@ static int cik_gpu_pci_config_reset(struct amdgpu_device *adev)
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return r;
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return r;
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}
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}
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static void cik_set_bios_scratch_engine_hung(struct amdgpu_device *adev, bool hung)
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{
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u32 tmp = RREG32(mmBIOS_SCRATCH_3);
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if (hung)
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tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG;
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else
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tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG;
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WREG32(mmBIOS_SCRATCH_3, tmp);
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}
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/**
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/**
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* cik_asic_reset - soft reset GPU
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* cik_asic_reset - soft reset GPU
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*
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*
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@ -1213,11 +1201,12 @@ static void cik_set_bios_scratch_engine_hung(struct amdgpu_device *adev, bool hu
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static int cik_asic_reset(struct amdgpu_device *adev)
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static int cik_asic_reset(struct amdgpu_device *adev)
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{
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{
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int r;
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int r;
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cik_set_bios_scratch_engine_hung(adev, true);
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amdgpu_atombios_scratch_regs_engine_hung(adev, true);
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r = cik_gpu_pci_config_reset(adev);
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r = cik_gpu_pci_config_reset(adev);
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cik_set_bios_scratch_engine_hung(adev, false);
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amdgpu_atombios_scratch_regs_engine_hung(adev, false);
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return r;
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return r;
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}
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}
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@ -729,18 +729,6 @@ static int vi_gpu_pci_config_reset(struct amdgpu_device *adev)
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return -EINVAL;
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return -EINVAL;
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}
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}
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static void vi_set_bios_scratch_engine_hung(struct amdgpu_device *adev, bool hung)
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{
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u32 tmp = RREG32(mmBIOS_SCRATCH_3);
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if (hung)
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tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG;
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else
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tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG;
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WREG32(mmBIOS_SCRATCH_3, tmp);
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}
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/**
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/**
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* vi_asic_reset - soft reset GPU
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* vi_asic_reset - soft reset GPU
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*
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*
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@ -754,11 +742,11 @@ static int vi_asic_reset(struct amdgpu_device *adev)
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{
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{
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int r;
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int r;
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vi_set_bios_scratch_engine_hung(adev, true);
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amdgpu_atombios_scratch_regs_engine_hung(adev, true);
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r = vi_gpu_pci_config_reset(adev);
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r = vi_gpu_pci_config_reset(adev);
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vi_set_bios_scratch_engine_hung(adev, false);
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amdgpu_atombios_scratch_regs_engine_hung(adev, false);
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return r;
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return r;
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}
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}
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