KVM: arm/arm64: vgic-new: Add GICv3 redistributor IIDR and TYPER handler
The redistributor TYPER tells the OS about the associated MPIDR, also the LAST bit is crucial to determine the number of redistributors. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
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@ -22,6 +22,13 @@
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#include "vgic.h"
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#include "vgic-mmio.h"
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/* extract @num bytes at @offset bytes offset in data */
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static unsigned long extract_bytes(unsigned long data, unsigned int offset,
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unsigned int num)
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{
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return (data >> (offset * 8)) & GENMASK_ULL(num * 8 - 1, 0);
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}
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static unsigned long vgic_mmio_read_v3_misc(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len)
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{
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@ -68,6 +75,27 @@ static void vgic_mmio_write_v3_misc(struct kvm_vcpu *vcpu,
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}
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}
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static unsigned long vgic_mmio_read_v3r_typer(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len)
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{
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unsigned long mpidr = kvm_vcpu_get_mpidr_aff(vcpu);
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int target_vcpu_id = vcpu->vcpu_id;
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u64 value;
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value = (mpidr & GENMASK(23, 0)) << 32;
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value |= ((target_vcpu_id & 0xffff) << 8);
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if (target_vcpu_id == atomic_read(&vcpu->kvm->online_vcpus) - 1)
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value |= GICR_TYPER_LAST;
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return extract_bytes(value, addr & 7, len);
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}
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static unsigned long vgic_mmio_read_v3r_iidr(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len)
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{
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return (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0);
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}
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/*
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* The GICv3 per-IRQ registers are split to control PPIs and SGIs in the
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* redistributors, while SPIs are covered by registers in the distributor
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@ -142,10 +170,10 @@ static const struct vgic_register_region vgic_v3_rdbase_registers[] = {
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vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_LENGTH(GICR_IIDR,
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vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
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vgic_mmio_read_v3r_iidr, vgic_mmio_write_wi, 4,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_LENGTH(GICR_TYPER,
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vgic_mmio_read_raz, vgic_mmio_write_wi, 8,
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vgic_mmio_read_v3r_typer, vgic_mmio_write_wi, 8,
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VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_LENGTH(GICR_PROPBASER,
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vgic_mmio_read_raz, vgic_mmio_write_wi, 8,
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