drm/i915: clean up dsi pll calculation
Improve readability. No functional changes. v2: use more rational types (Ville) Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -162,53 +162,34 @@ static u32 dsi_clk_from_pclk(u32 pclk, int pixel_format, int lane_count)
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#endif
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#endif
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static int dsi_calc_mnp(u32 dsi_clk, struct dsi_mnp *dsi_mnp)
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static int dsi_calc_mnp(int target_dsi_clk, struct dsi_mnp *dsi_mnp)
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{
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{
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u32 m, n, p;
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unsigned int calc_m = 0, calc_p = 0;
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u32 ref_clk;
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unsigned int m, n, p;
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u32 error;
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int ref_clk = 25000;
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u32 tmp_error;
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int delta = target_dsi_clk;
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int target_dsi_clk;
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int calc_dsi_clk;
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u32 calc_m;
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u32 calc_p;
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u32 m_seed;
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u32 m_seed;
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/* dsi_clk is expected in KHZ */
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/* target_dsi_clk is expected in kHz */
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if (dsi_clk < 300000 || dsi_clk > 1150000) {
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if (target_dsi_clk < 300000 || target_dsi_clk > 1150000) {
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DRM_ERROR("DSI CLK Out of Range\n");
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DRM_ERROR("DSI CLK Out of Range\n");
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return -ECHRNG;
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return -ECHRNG;
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}
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}
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ref_clk = 25000;
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for (m = 62; m <= 92 && delta; m++) {
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target_dsi_clk = dsi_clk;
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for (p = 2; p <= 6 && delta; p++) {
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error = 0xFFFFFFFF;
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/*
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tmp_error = 0xFFFFFFFF;
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* Find the optimal m and p divisors with minimal delta
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calc_m = 0;
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* +/- the required clock
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calc_p = 0;
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*/
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int calc_dsi_clk = (m * ref_clk) / p;
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for (m = 62; m <= 92; m++) {
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int d = abs(target_dsi_clk - calc_dsi_clk);
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for (p = 2; p <= 6; p++) {
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if (d < delta) {
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/* Find the optimal m and p divisors
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delta = d;
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with minimal error +/- the required clock */
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calc_dsi_clk = (m * ref_clk) / p;
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if (calc_dsi_clk == target_dsi_clk) {
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calc_m = m;
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calc_p = p;
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error = 0;
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break;
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} else
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tmp_error = abs(target_dsi_clk - calc_dsi_clk);
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if (tmp_error < error) {
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error = tmp_error;
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calc_m = m;
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calc_m = m;
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calc_p = p;
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calc_p = p;
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}
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}
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}
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}
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if (error == 0)
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break;
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}
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}
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m_seed = lfsr_converts[calc_m - 62];
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m_seed = lfsr_converts[calc_m - 62];
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