ARM: dts: r8a7779: Use SYSC "always-on" PM Domain
Hook up all devices that are part of the CPG/MSTP Clock Domain to the SYSC "always-on" PM Domain, for a more consistent device-power-area description in DT. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Geert Uytterhoeven
Simon Horman
parent
0761ff2ad0
commit
751e29bbb6
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@ -177,7 +177,7 @@ i2c0: i2c@ffc70000 {
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reg = <0xffc70000 0x1000>;
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interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp0_clks R8A7779_CLK_I2C0>;
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power-domains = <&cpg_clocks>;
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power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
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status = "disabled";
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};
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@ -188,7 +188,7 @@ i2c1: i2c@ffc71000 {
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reg = <0xffc71000 0x1000>;
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interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp0_clks R8A7779_CLK_I2C1>;
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power-domains = <&cpg_clocks>;
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power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
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status = "disabled";
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};
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@ -199,7 +199,7 @@ i2c2: i2c@ffc72000 {
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reg = <0xffc72000 0x1000>;
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interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp0_clks R8A7779_CLK_I2C2>;
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power-domains = <&cpg_clocks>;
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power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
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status = "disabled";
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};
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@ -210,7 +210,7 @@ i2c3: i2c@ffc73000 {
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reg = <0xffc73000 0x1000>;
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interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp0_clks R8A7779_CLK_I2C3>;
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power-domains = <&cpg_clocks>;
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power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
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status = "disabled";
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};
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@ -222,7 +222,7 @@ scif0: serial@ffe40000 {
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clocks = <&mstp0_clks R8A7779_CLK_SCIF0>,
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<&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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power-domains = <&cpg_clocks>;
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power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
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status = "disabled";
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};
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@ -234,7 +234,7 @@ scif1: serial@ffe41000 {
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clocks = <&mstp0_clks R8A7779_CLK_SCIF1>,
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<&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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power-domains = <&cpg_clocks>;
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power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
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status = "disabled";
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};
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@ -246,7 +246,7 @@ scif2: serial@ffe42000 {
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clocks = <&mstp0_clks R8A7779_CLK_SCIF2>,
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<&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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power-domains = <&cpg_clocks>;
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power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
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status = "disabled";
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};
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@ -258,7 +258,7 @@ scif3: serial@ffe43000 {
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clocks = <&mstp0_clks R8A7779_CLK_SCIF3>,
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<&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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power-domains = <&cpg_clocks>;
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power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
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status = "disabled";
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};
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@ -270,7 +270,7 @@ scif4: serial@ffe44000 {
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clocks = <&mstp0_clks R8A7779_CLK_SCIF4>,
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<&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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power-domains = <&cpg_clocks>;
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power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
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status = "disabled";
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};
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@ -282,7 +282,7 @@ scif5: serial@ffe45000 {
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clocks = <&mstp0_clks R8A7779_CLK_SCIF5>,
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<&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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power-domains = <&cpg_clocks>;
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power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
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status = "disabled";
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};
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@ -304,7 +304,7 @@ tmu0: timer@ffd80000 {
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<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp0_clks R8A7779_CLK_TMU0>;
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clock-names = "fck";
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power-domains = <&cpg_clocks>;
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power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
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#renesas,channels = <3>;
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@ -319,7 +319,7 @@ tmu1: timer@ffd81000 {
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<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp0_clks R8A7779_CLK_TMU1>;
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clock-names = "fck";
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power-domains = <&cpg_clocks>;
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power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
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#renesas,channels = <3>;
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@ -334,7 +334,7 @@ tmu2: timer@ffd82000 {
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<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp0_clks R8A7779_CLK_TMU2>;
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clock-names = "fck";
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power-domains = <&cpg_clocks>;
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power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
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#renesas,channels = <3>;
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@ -346,7 +346,7 @@ sata: sata@fc600000 {
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reg = <0xfc600000 0x2000>;
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interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp1_clks R8A7779_CLK_SATA>;
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power-domains = <&cpg_clocks>;
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power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
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};
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sdhi0: sd@ffe4c000 {
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@ -354,7 +354,7 @@ sdhi0: sd@ffe4c000 {
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reg = <0xffe4c000 0x100>;
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interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A7779_CLK_SDHI0>;
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power-domains = <&cpg_clocks>;
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power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
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status = "disabled";
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};
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@ -363,7 +363,7 @@ sdhi1: sd@ffe4d000 {
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reg = <0xffe4d000 0x100>;
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interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A7779_CLK_SDHI1>;
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power-domains = <&cpg_clocks>;
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power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
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status = "disabled";
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};
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@ -372,7 +372,7 @@ sdhi2: sd@ffe4e000 {
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reg = <0xffe4e000 0x100>;
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interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A7779_CLK_SDHI2>;
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power-domains = <&cpg_clocks>;
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power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
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status = "disabled";
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};
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@ -381,7 +381,7 @@ sdhi3: sd@ffe4f000 {
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reg = <0xffe4f000 0x100>;
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interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A7779_CLK_SDHI3>;
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power-domains = <&cpg_clocks>;
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power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
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status = "disabled";
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};
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@ -392,7 +392,7 @@ hspi0: spi@fffc7000 {
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
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power-domains = <&cpg_clocks>;
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power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
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status = "disabled";
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};
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@ -403,7 +403,7 @@ hspi1: spi@fffc8000 {
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
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power-domains = <&cpg_clocks>;
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power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
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status = "disabled";
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};
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@ -414,7 +414,7 @@ hspi2: spi@fffc6000 {
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
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power-domains = <&cpg_clocks>;
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power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
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status = "disabled";
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};
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@ -423,7 +423,7 @@ du: display@fff80000 {
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reg = <0 0xfff80000 0 0x40000>;
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interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp1_clks R8A7779_CLK_DU>;
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power-domains = <&cpg_clocks>;
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power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
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status = "disabled";
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ports {
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