bnxt_en: Keep track of reserved IRQs.
The new 57500 chips use 1 NQ per MSIX vector, whereas legacy chips use 1 CP ring per MSIX vector. To better unify this, add a resv_irqs field to struct bnxt_hw_resc. On legacy chips, we initialize resv_irqs with resv_cp_rings. On new chips, we initialize it with the allocated MSIX resources. Signed-off-by: Michael Chan <michael.chan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -5162,6 +5162,7 @@ static int bnxt_hwrm_get_rings(struct bnxt *bp)
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cp = le16_to_cpu(resp->alloc_cmpl_rings);
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cp = le16_to_cpu(resp->alloc_cmpl_rings);
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stats = le16_to_cpu(resp->alloc_stat_ctx);
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stats = le16_to_cpu(resp->alloc_stat_ctx);
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cp = min_t(u16, cp, stats);
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cp = min_t(u16, cp, stats);
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hw_resc->resv_irqs = cp;
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if (bp->flags & BNXT_FLAG_CHIP_P5) {
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if (bp->flags & BNXT_FLAG_CHIP_P5) {
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int rx = hw_resc->resv_rx_rings;
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int rx = hw_resc->resv_rx_rings;
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int tx = hw_resc->resv_tx_rings;
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int tx = hw_resc->resv_tx_rings;
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@ -5175,7 +5176,7 @@ static int bnxt_hwrm_get_rings(struct bnxt *bp)
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hw_resc->resv_rx_rings = rx;
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hw_resc->resv_rx_rings = rx;
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hw_resc->resv_tx_rings = tx;
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hw_resc->resv_tx_rings = tx;
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}
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}
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cp = le16_to_cpu(resp->alloc_msix);
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hw_resc->resv_irqs = le16_to_cpu(resp->alloc_msix);
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hw_resc->resv_hw_ring_grps = rx;
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hw_resc->resv_hw_ring_grps = rx;
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}
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}
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hw_resc->resv_cp_rings = cp;
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hw_resc->resv_cp_rings = cp;
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@ -7055,7 +7056,9 @@ int bnxt_get_avail_msix(struct bnxt *bp, int num)
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int total_req = bp->cp_nr_rings + num;
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int total_req = bp->cp_nr_rings + num;
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int max_idx, avail_msix;
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int max_idx, avail_msix;
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max_idx = min_t(int, bp->total_irqs, max_cp);
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max_idx = bp->total_irqs;
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if (!(bp->flags & BNXT_FLAG_CHIP_P5))
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max_idx = min_t(int, bp->total_irqs, max_cp);
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avail_msix = max_idx - bp->cp_nr_rings;
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avail_msix = max_idx - bp->cp_nr_rings;
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if (!BNXT_NEW_RM(bp) || avail_msix >= num)
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if (!BNXT_NEW_RM(bp) || avail_msix >= num)
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return avail_msix;
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return avail_msix;
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@ -7801,6 +7804,7 @@ static int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
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rc = bnxt_hwrm_func_resc_qcaps(bp, true);
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rc = bnxt_hwrm_func_resc_qcaps(bp, true);
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hw_resc->resv_cp_rings = 0;
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hw_resc->resv_cp_rings = 0;
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hw_resc->resv_irqs = 0;
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hw_resc->resv_tx_rings = 0;
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hw_resc->resv_tx_rings = 0;
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hw_resc->resv_rx_rings = 0;
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hw_resc->resv_rx_rings = 0;
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hw_resc->resv_hw_ring_grps = 0;
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hw_resc->resv_hw_ring_grps = 0;
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@ -928,6 +928,7 @@ struct bnxt_hw_resc {
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u16 min_stat_ctxs;
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u16 min_stat_ctxs;
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u16 max_stat_ctxs;
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u16 max_stat_ctxs;
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u16 max_irqs;
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u16 max_irqs;
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u16 resv_irqs;
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};
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};
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#if defined(CONFIG_BNXT_SRIOV)
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#if defined(CONFIG_BNXT_SRIOV)
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@ -168,7 +168,7 @@ static int bnxt_req_msix_vecs(struct bnxt_en_dev *edev, int ulp_id,
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if (BNXT_NEW_RM(bp)) {
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if (BNXT_NEW_RM(bp)) {
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struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
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struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
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avail_msix = hw_resc->resv_cp_rings - bp->cp_nr_rings;
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avail_msix = hw_resc->resv_irqs - bp->cp_nr_rings;
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edev->ulp_tbl[ulp_id].msix_requested = avail_msix;
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edev->ulp_tbl[ulp_id].msix_requested = avail_msix;
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}
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}
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bnxt_fill_msix_vecs(bp, ent);
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bnxt_fill_msix_vecs(bp, ent);
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