pinctrl: sh-pfc: r8a7779: use PINMUX_IPSR_MSEL()
Now, PINMUX_IPSR_MSEL() and PINMUX_IPSR_MODSEL_DATA() are same. Current PFC driver is very difficult to read, because macro names are using different length. PINMUX_IPSR_NOGP(ispr, ...) PINMUX_IPSR_DATA(ipsr, ...) PINMUX_IPSR_NOGM(ispr, ...) PINMUX_IPSR_NOFN(ipsr, ...) PINMUX_IPSR_MSEL(ipsr, ...) PINMUX_IPSR_MODSEL_DATA(ipsr, ...) It can be readable if we can use PINMUX_IPSR_MSEL() instead of PINMUX_IPSR_MODSEL_DATA() PINMUX_IPSR_NOGP(ispr, ...) PINMUX_IPSR_DATA(ipsr, ...) PINMUX_IPSR_NOGM(ispr, ...) PINMUX_IPSR_NOFN(ipsr, ...) PINMUX_IPSR_MSEL(ipsr, ...) Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Kuninori Morimoto
Geert Uytterhoeven
parent
af5132dd12
commit
759151401c
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@ -620,18 +620,18 @@ static const u16 pinmux_data[] = {
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PINMUX_DATA(USB_PENC1_MARK, FN_USB_PENC1),
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PINMUX_IPSR_DATA(IP0_2_0, USB_PENC2),
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PINMUX_IPSR_MODSEL_DATA(IP0_2_0, SCK0, SEL_SCIF0_0),
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PINMUX_IPSR_MSEL(IP0_2_0, SCK0, SEL_SCIF0_0),
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PINMUX_IPSR_DATA(IP0_2_0, PWM1),
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PINMUX_IPSR_MODSEL_DATA(IP0_2_0, PWMFSW0, SEL_PWMFSW_0),
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PINMUX_IPSR_MODSEL_DATA(IP0_2_0, SCIF_CLK, SEL_SCIF_0),
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PINMUX_IPSR_MODSEL_DATA(IP0_2_0, TCLK0_C, SEL_TMU0_2),
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PINMUX_IPSR_MSEL(IP0_2_0, PWMFSW0, SEL_PWMFSW_0),
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PINMUX_IPSR_MSEL(IP0_2_0, SCIF_CLK, SEL_SCIF_0),
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PINMUX_IPSR_MSEL(IP0_2_0, TCLK0_C, SEL_TMU0_2),
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PINMUX_IPSR_DATA(IP0_5_3, BS),
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PINMUX_IPSR_DATA(IP0_5_3, SD1_DAT2),
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PINMUX_IPSR_DATA(IP0_5_3, MMC0_D2),
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PINMUX_IPSR_DATA(IP0_5_3, FD2),
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PINMUX_IPSR_DATA(IP0_5_3, ATADIR0),
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PINMUX_IPSR_DATA(IP0_5_3, SDSELF),
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PINMUX_IPSR_MODSEL_DATA(IP0_5_3, HCTS1, SEL_HSCIF1_0),
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PINMUX_IPSR_MSEL(IP0_5_3, HCTS1, SEL_HSCIF1_0),
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PINMUX_IPSR_DATA(IP0_5_3, TX4_C),
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PINMUX_IPSR_DATA(IP0_7_6, A0),
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PINMUX_IPSR_DATA(IP0_7_6, SD1_DAT3),
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@ -641,37 +641,37 @@ static const u16 pinmux_data[] = {
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PINMUX_IPSR_DATA(IP0_9_8, TX5_D),
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PINMUX_IPSR_DATA(IP0_9_8, HSPI_TX2_B),
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PINMUX_IPSR_DATA(IP0_11_10, A21),
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PINMUX_IPSR_MODSEL_DATA(IP0_11_10, SCK5_D, SEL_SCIF5_3),
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PINMUX_IPSR_MODSEL_DATA(IP0_11_10, HSPI_CLK2_B, SEL_HSPI2_1),
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PINMUX_IPSR_MSEL(IP0_11_10, SCK5_D, SEL_SCIF5_3),
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PINMUX_IPSR_MSEL(IP0_11_10, HSPI_CLK2_B, SEL_HSPI2_1),
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PINMUX_IPSR_DATA(IP0_13_12, A22),
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PINMUX_IPSR_MODSEL_DATA(IP0_13_12, RX5_D, SEL_SCIF5_3),
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PINMUX_IPSR_MODSEL_DATA(IP0_13_12, HSPI_RX2_B, SEL_HSPI2_1),
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PINMUX_IPSR_MSEL(IP0_13_12, RX5_D, SEL_SCIF5_3),
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PINMUX_IPSR_MSEL(IP0_13_12, HSPI_RX2_B, SEL_HSPI2_1),
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PINMUX_IPSR_DATA(IP0_13_12, VI1_R0),
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PINMUX_IPSR_DATA(IP0_15_14, A23),
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PINMUX_IPSR_DATA(IP0_15_14, FCLE),
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PINMUX_IPSR_MODSEL_DATA(IP0_15_14, HSPI_CLK2, SEL_HSPI2_0),
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PINMUX_IPSR_MSEL(IP0_15_14, HSPI_CLK2, SEL_HSPI2_0),
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PINMUX_IPSR_DATA(IP0_15_14, VI1_R1),
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PINMUX_IPSR_DATA(IP0_18_16, A24),
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PINMUX_IPSR_DATA(IP0_18_16, SD1_CD),
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PINMUX_IPSR_DATA(IP0_18_16, MMC0_D4),
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PINMUX_IPSR_DATA(IP0_18_16, FD4),
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PINMUX_IPSR_MODSEL_DATA(IP0_18_16, HSPI_CS2, SEL_HSPI2_0),
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PINMUX_IPSR_MSEL(IP0_18_16, HSPI_CS2, SEL_HSPI2_0),
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PINMUX_IPSR_DATA(IP0_18_16, VI1_R2),
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PINMUX_IPSR_MODSEL_DATA(IP0_18_16, SSI_WS78_B, SEL_SSI7_1),
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PINMUX_IPSR_MSEL(IP0_18_16, SSI_WS78_B, SEL_SSI7_1),
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PINMUX_IPSR_DATA(IP0_22_19, A25),
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PINMUX_IPSR_DATA(IP0_22_19, SD1_WP),
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PINMUX_IPSR_DATA(IP0_22_19, MMC0_D5),
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PINMUX_IPSR_DATA(IP0_22_19, FD5),
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PINMUX_IPSR_MODSEL_DATA(IP0_22_19, HSPI_RX2, SEL_HSPI2_0),
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PINMUX_IPSR_MSEL(IP0_22_19, HSPI_RX2, SEL_HSPI2_0),
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PINMUX_IPSR_DATA(IP0_22_19, VI1_R3),
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PINMUX_IPSR_DATA(IP0_22_19, TX5_B),
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PINMUX_IPSR_MODSEL_DATA(IP0_22_19, SSI_SDATA7_B, SEL_SSI7_1),
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PINMUX_IPSR_MODSEL_DATA(IP0_22_19, CTS0_B, SEL_SCIF0_1),
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PINMUX_IPSR_MSEL(IP0_22_19, SSI_SDATA7_B, SEL_SSI7_1),
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PINMUX_IPSR_MSEL(IP0_22_19, CTS0_B, SEL_SCIF0_1),
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PINMUX_IPSR_DATA(IP0_24_23, CLKOUT),
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PINMUX_IPSR_DATA(IP0_24_23, TX3C_IRDA_TX_C),
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PINMUX_IPSR_DATA(IP0_24_23, PWM0_B),
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PINMUX_IPSR_DATA(IP0_25, CS0),
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PINMUX_IPSR_MODSEL_DATA(IP0_25, HSPI_CS2_B, SEL_HSPI2_1),
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PINMUX_IPSR_MSEL(IP0_25, HSPI_CS2_B, SEL_HSPI2_1),
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PINMUX_IPSR_DATA(IP0_27_26, CS1_A26),
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PINMUX_IPSR_DATA(IP0_27_26, HSPI_TX2),
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PINMUX_IPSR_DATA(IP0_27_26, SDSELF_B),
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@ -679,11 +679,11 @@ static const u16 pinmux_data[] = {
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PINMUX_IPSR_DATA(IP0_30_28, FWE),
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PINMUX_IPSR_DATA(IP0_30_28, ATAG0),
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PINMUX_IPSR_DATA(IP0_30_28, VI1_R7),
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PINMUX_IPSR_MODSEL_DATA(IP0_30_28, HRTS1, SEL_HSCIF1_0),
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PINMUX_IPSR_MODSEL_DATA(IP0_30_28, RX4_C, SEL_SCIF4_2),
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PINMUX_IPSR_MSEL(IP0_30_28, HRTS1, SEL_HSCIF1_0),
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PINMUX_IPSR_MSEL(IP0_30_28, RX4_C, SEL_SCIF4_2),
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PINMUX_IPSR_DATA(IP1_1_0, EX_CS0),
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PINMUX_IPSR_MODSEL_DATA(IP1_1_0, RX3_C_IRDA_RX_C, SEL_SCIF3_2),
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PINMUX_IPSR_MSEL(IP1_1_0, RX3_C_IRDA_RX_C, SEL_SCIF3_2),
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PINMUX_IPSR_DATA(IP1_1_0, MMC0_D6),
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PINMUX_IPSR_DATA(IP1_1_0, FD6),
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PINMUX_IPSR_DATA(IP1_3_2, EX_CS1),
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@ -700,45 +700,45 @@ static const u16 pinmux_data[] = {
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PINMUX_IPSR_DATA(IP1_10_7, FRE),
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PINMUX_IPSR_DATA(IP1_10_7, ATACS10),
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PINMUX_IPSR_DATA(IP1_10_7, VI1_R4),
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PINMUX_IPSR_MODSEL_DATA(IP1_10_7, RX5_B, SEL_SCIF5_1),
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PINMUX_IPSR_MODSEL_DATA(IP1_10_7, HSCK1, SEL_HSCIF1_0),
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PINMUX_IPSR_MODSEL_DATA(IP1_10_7, SSI_SDATA8_B, SEL_SSI8_1),
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PINMUX_IPSR_MODSEL_DATA(IP1_10_7, RTS0_B_TANS_B, SEL_SCIF0_1),
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PINMUX_IPSR_MODSEL_DATA(IP1_10_7, SSI_SDATA9, SEL_SSI9_0),
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PINMUX_IPSR_MSEL(IP1_10_7, RX5_B, SEL_SCIF5_1),
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PINMUX_IPSR_MSEL(IP1_10_7, HSCK1, SEL_HSCIF1_0),
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PINMUX_IPSR_MSEL(IP1_10_7, SSI_SDATA8_B, SEL_SSI8_1),
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PINMUX_IPSR_MSEL(IP1_10_7, RTS0_B_TANS_B, SEL_SCIF0_1),
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PINMUX_IPSR_MSEL(IP1_10_7, SSI_SDATA9, SEL_SSI9_0),
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PINMUX_IPSR_DATA(IP1_14_11, EX_CS4),
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PINMUX_IPSR_DATA(IP1_14_11, SD1_DAT0),
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PINMUX_IPSR_DATA(IP1_14_11, MMC0_D0),
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PINMUX_IPSR_DATA(IP1_14_11, FD0),
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PINMUX_IPSR_DATA(IP1_14_11, ATARD0),
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PINMUX_IPSR_DATA(IP1_14_11, VI1_R5),
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PINMUX_IPSR_MODSEL_DATA(IP1_14_11, SCK5_B, SEL_SCIF5_1),
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PINMUX_IPSR_MSEL(IP1_14_11, SCK5_B, SEL_SCIF5_1),
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PINMUX_IPSR_DATA(IP1_14_11, HTX1),
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PINMUX_IPSR_DATA(IP1_14_11, TX2_E),
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PINMUX_IPSR_DATA(IP1_14_11, TX0_B),
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PINMUX_IPSR_MODSEL_DATA(IP1_14_11, SSI_SCK9, SEL_SSI9_0),
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PINMUX_IPSR_MSEL(IP1_14_11, SSI_SCK9, SEL_SSI9_0),
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PINMUX_IPSR_DATA(IP1_18_15, EX_CS5),
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PINMUX_IPSR_DATA(IP1_18_15, SD1_DAT1),
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PINMUX_IPSR_DATA(IP1_18_15, MMC0_D1),
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PINMUX_IPSR_DATA(IP1_18_15, FD1),
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PINMUX_IPSR_DATA(IP1_18_15, ATAWR0),
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PINMUX_IPSR_DATA(IP1_18_15, VI1_R6),
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PINMUX_IPSR_MODSEL_DATA(IP1_18_15, HRX1, SEL_HSCIF1_0),
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PINMUX_IPSR_MODSEL_DATA(IP1_18_15, RX2_E, SEL_SCIF2_4),
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PINMUX_IPSR_MODSEL_DATA(IP1_18_15, RX0_B, SEL_SCIF0_1),
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PINMUX_IPSR_MODSEL_DATA(IP1_18_15, SSI_WS9, SEL_SSI9_0),
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PINMUX_IPSR_MSEL(IP1_18_15, HRX1, SEL_HSCIF1_0),
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PINMUX_IPSR_MSEL(IP1_18_15, RX2_E, SEL_SCIF2_4),
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PINMUX_IPSR_MSEL(IP1_18_15, RX0_B, SEL_SCIF0_1),
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PINMUX_IPSR_MSEL(IP1_18_15, SSI_WS9, SEL_SSI9_0),
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PINMUX_IPSR_DATA(IP1_20_19, MLB_CLK),
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PINMUX_IPSR_DATA(IP1_20_19, PWM2),
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PINMUX_IPSR_MODSEL_DATA(IP1_20_19, SCK4, SEL_SCIF4_0),
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PINMUX_IPSR_MSEL(IP1_20_19, SCK4, SEL_SCIF4_0),
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PINMUX_IPSR_DATA(IP1_22_21, MLB_SIG),
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PINMUX_IPSR_DATA(IP1_22_21, PWM3),
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PINMUX_IPSR_DATA(IP1_22_21, TX4),
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PINMUX_IPSR_DATA(IP1_24_23, MLB_DAT),
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PINMUX_IPSR_DATA(IP1_24_23, PWM4),
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PINMUX_IPSR_MODSEL_DATA(IP1_24_23, RX4, SEL_SCIF4_0),
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PINMUX_IPSR_MSEL(IP1_24_23, RX4, SEL_SCIF4_0),
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PINMUX_IPSR_DATA(IP1_28_25, HTX0),
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PINMUX_IPSR_DATA(IP1_28_25, TX1),
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PINMUX_IPSR_DATA(IP1_28_25, SDATA),
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PINMUX_IPSR_MODSEL_DATA(IP1_28_25, CTS0_C, SEL_SCIF0_2),
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PINMUX_IPSR_MSEL(IP1_28_25, CTS0_C, SEL_SCIF0_2),
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PINMUX_IPSR_DATA(IP1_28_25, SUB_TCK),
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PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE2),
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PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE10),
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@ -746,39 +746,39 @@ static const u16 pinmux_data[] = {
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PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE26),
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PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE34),
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PINMUX_IPSR_MODSEL_DATA(IP2_3_0, HRX0, SEL_HSCIF0_0),
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PINMUX_IPSR_MODSEL_DATA(IP2_3_0, RX1, SEL_SCIF1_0),
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PINMUX_IPSR_MSEL(IP2_3_0, HRX0, SEL_HSCIF0_0),
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PINMUX_IPSR_MSEL(IP2_3_0, RX1, SEL_SCIF1_0),
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PINMUX_IPSR_DATA(IP2_3_0, SCKZ),
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PINMUX_IPSR_MODSEL_DATA(IP2_3_0, RTS0_C_TANS_C, SEL_SCIF0_2),
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PINMUX_IPSR_MSEL(IP2_3_0, RTS0_C_TANS_C, SEL_SCIF0_2),
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PINMUX_IPSR_DATA(IP2_3_0, SUB_TDI),
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PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE3),
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PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE11),
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PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE19),
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PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE27),
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PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE35),
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PINMUX_IPSR_MODSEL_DATA(IP2_7_4, HSCK0, SEL_HSCIF0_0),
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PINMUX_IPSR_MODSEL_DATA(IP2_7_4, SCK1, SEL_SCIF1_0),
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PINMUX_IPSR_MSEL(IP2_7_4, HSCK0, SEL_HSCIF0_0),
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PINMUX_IPSR_MSEL(IP2_7_4, SCK1, SEL_SCIF1_0),
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PINMUX_IPSR_DATA(IP2_7_4, MTS),
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PINMUX_IPSR_DATA(IP2_7_4, PWM5),
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PINMUX_IPSR_MODSEL_DATA(IP2_7_4, SCK0_C, SEL_SCIF0_2),
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PINMUX_IPSR_MODSEL_DATA(IP2_7_4, SSI_SDATA9_B, SEL_SSI9_1),
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PINMUX_IPSR_MSEL(IP2_7_4, SCK0_C, SEL_SCIF0_2),
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PINMUX_IPSR_MSEL(IP2_7_4, SSI_SDATA9_B, SEL_SSI9_1),
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PINMUX_IPSR_DATA(IP2_7_4, SUB_TDO),
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PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE0),
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PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE8),
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PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE16),
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PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE24),
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PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE32),
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PINMUX_IPSR_MODSEL_DATA(IP2_11_8, HCTS0, SEL_HSCIF0_0),
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PINMUX_IPSR_MODSEL_DATA(IP2_11_8, CTS1, SEL_SCIF1_0),
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PINMUX_IPSR_MSEL(IP2_11_8, HCTS0, SEL_HSCIF0_0),
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PINMUX_IPSR_MSEL(IP2_11_8, CTS1, SEL_SCIF1_0),
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PINMUX_IPSR_DATA(IP2_11_8, STM),
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PINMUX_IPSR_DATA(IP2_11_8, PWM0_D),
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PINMUX_IPSR_MODSEL_DATA(IP2_11_8, RX0_C, SEL_SCIF0_2),
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PINMUX_IPSR_MODSEL_DATA(IP2_11_8, SCIF_CLK_C, SEL_SCIF_2),
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PINMUX_IPSR_MSEL(IP2_11_8, RX0_C, SEL_SCIF0_2),
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PINMUX_IPSR_MSEL(IP2_11_8, SCIF_CLK_C, SEL_SCIF_2),
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PINMUX_IPSR_DATA(IP2_11_8, SUB_TRST),
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PINMUX_IPSR_MODSEL_DATA(IP2_11_8, TCLK1_B, SEL_TMU1_1),
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PINMUX_IPSR_MSEL(IP2_11_8, TCLK1_B, SEL_TMU1_1),
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PINMUX_IPSR_DATA(IP2_11_8, CC5_OSCOUT),
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PINMUX_IPSR_MODSEL_DATA(IP2_15_12, HRTS0, SEL_HSCIF0_0),
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PINMUX_IPSR_MODSEL_DATA(IP2_15_12, RTS1_TANS, SEL_SCIF1_0),
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PINMUX_IPSR_MSEL(IP2_15_12, HRTS0, SEL_HSCIF0_0),
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PINMUX_IPSR_MSEL(IP2_15_12, RTS1_TANS, SEL_SCIF1_0),
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PINMUX_IPSR_DATA(IP2_15_12, MDATA),
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PINMUX_IPSR_DATA(IP2_15_12, TX0_C),
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PINMUX_IPSR_DATA(IP2_15_12, SUB_TMS),
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@ -789,17 +789,17 @@ static const u16 pinmux_data[] = {
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PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE33),
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PINMUX_IPSR_DATA(IP2_18_16, DU0_DR0),
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PINMUX_IPSR_DATA(IP2_18_16, LCDOUT0),
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PINMUX_IPSR_MODSEL_DATA(IP2_18_16, DREQ0, SEL_EXBUS0_0),
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PINMUX_IPSR_MODSEL_DATA(IP2_18_16, GPS_CLK_B, SEL_GPS_1),
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PINMUX_IPSR_MSEL(IP2_18_16, DREQ0, SEL_EXBUS0_0),
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PINMUX_IPSR_MSEL(IP2_18_16, GPS_CLK_B, SEL_GPS_1),
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PINMUX_IPSR_DATA(IP2_18_16, AUDATA0),
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PINMUX_IPSR_DATA(IP2_18_16, TX5_C),
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PINMUX_IPSR_DATA(IP2_21_19, DU0_DR1),
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PINMUX_IPSR_DATA(IP2_21_19, LCDOUT1),
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PINMUX_IPSR_DATA(IP2_21_19, DACK0),
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PINMUX_IPSR_DATA(IP2_21_19, DRACK0),
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PINMUX_IPSR_MODSEL_DATA(IP2_21_19, GPS_SIGN_B, SEL_GPS_1),
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PINMUX_IPSR_MSEL(IP2_21_19, GPS_SIGN_B, SEL_GPS_1),
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PINMUX_IPSR_DATA(IP2_21_19, AUDATA1),
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||||
PINMUX_IPSR_MODSEL_DATA(IP2_21_19, RX5_C, SEL_SCIF5_2),
|
||||
PINMUX_IPSR_MSEL(IP2_21_19, RX5_C, SEL_SCIF5_2),
|
||||
PINMUX_IPSR_DATA(IP2_22, DU0_DR2),
|
||||
PINMUX_IPSR_DATA(IP2_22, LCDOUT2),
|
||||
PINMUX_IPSR_DATA(IP2_23, DU0_DR3),
|
||||
|
|
@ -814,14 +814,14 @@ static const u16 pinmux_data[] = {
|
|||
PINMUX_IPSR_DATA(IP2_27, LCDOUT7),
|
||||
PINMUX_IPSR_DATA(IP2_30_28, DU0_DG0),
|
||||
PINMUX_IPSR_DATA(IP2_30_28, LCDOUT8),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP2_30_28, DREQ1, SEL_EXBUS1_0),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP2_30_28, SCL2, SEL_I2C2_0),
|
||||
PINMUX_IPSR_MSEL(IP2_30_28, DREQ1, SEL_EXBUS1_0),
|
||||
PINMUX_IPSR_MSEL(IP2_30_28, SCL2, SEL_I2C2_0),
|
||||
PINMUX_IPSR_DATA(IP2_30_28, AUDATA2),
|
||||
|
||||
PINMUX_IPSR_DATA(IP3_2_0, DU0_DG1),
|
||||
PINMUX_IPSR_DATA(IP3_2_0, LCDOUT9),
|
||||
PINMUX_IPSR_DATA(IP3_2_0, DACK1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP3_2_0, SDA2, SEL_I2C2_0),
|
||||
PINMUX_IPSR_MSEL(IP3_2_0, SDA2, SEL_I2C2_0),
|
||||
PINMUX_IPSR_DATA(IP3_2_0, AUDATA3),
|
||||
PINMUX_IPSR_DATA(IP3_3, DU0_DG2),
|
||||
PINMUX_IPSR_DATA(IP3_3, LCDOUT10),
|
||||
|
|
@ -838,16 +838,16 @@ static const u16 pinmux_data[] = {
|
|||
PINMUX_IPSR_DATA(IP3_11_9, DU0_DB0),
|
||||
PINMUX_IPSR_DATA(IP3_11_9, LCDOUT16),
|
||||
PINMUX_IPSR_DATA(IP3_11_9, EX_WAIT1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP3_11_9, SCL1, SEL_I2C1_0),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP3_11_9, TCLK1, SEL_TMU1_0),
|
||||
PINMUX_IPSR_MSEL(IP3_11_9, SCL1, SEL_I2C1_0),
|
||||
PINMUX_IPSR_MSEL(IP3_11_9, TCLK1, SEL_TMU1_0),
|
||||
PINMUX_IPSR_DATA(IP3_11_9, AUDATA4),
|
||||
PINMUX_IPSR_DATA(IP3_14_12, DU0_DB1),
|
||||
PINMUX_IPSR_DATA(IP3_14_12, LCDOUT17),
|
||||
PINMUX_IPSR_DATA(IP3_14_12, EX_WAIT2),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP3_14_12, SDA1, SEL_I2C1_0),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP3_14_12, GPS_MAG_B, SEL_GPS_1),
|
||||
PINMUX_IPSR_MSEL(IP3_14_12, SDA1, SEL_I2C1_0),
|
||||
PINMUX_IPSR_MSEL(IP3_14_12, GPS_MAG_B, SEL_GPS_1),
|
||||
PINMUX_IPSR_DATA(IP3_14_12, AUDATA5),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP3_14_12, SCK5_C, SEL_SCIF5_2),
|
||||
PINMUX_IPSR_MSEL(IP3_14_12, SCK5_C, SEL_SCIF5_2),
|
||||
PINMUX_IPSR_DATA(IP3_15, DU0_DB2),
|
||||
PINMUX_IPSR_DATA(IP3_15, LCDOUT18),
|
||||
PINMUX_IPSR_DATA(IP3_16, DU0_DB3),
|
||||
|
|
@ -863,14 +863,14 @@ static const u16 pinmux_data[] = {
|
|||
PINMUX_IPSR_DATA(IP3_22_21, DU0_DOTCLKIN),
|
||||
PINMUX_IPSR_DATA(IP3_22_21, QSTVA_QVS),
|
||||
PINMUX_IPSR_DATA(IP3_22_21, TX3_D_IRDA_TX_D),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP3_22_21, SCL3_B, SEL_I2C3_1),
|
||||
PINMUX_IPSR_MSEL(IP3_22_21, SCL3_B, SEL_I2C3_1),
|
||||
PINMUX_IPSR_DATA(IP3_23, DU0_DOTCLKOUT0),
|
||||
PINMUX_IPSR_DATA(IP3_23, QCLK),
|
||||
PINMUX_IPSR_DATA(IP3_26_24, DU0_DOTCLKOUT1),
|
||||
PINMUX_IPSR_DATA(IP3_26_24, QSTVB_QVE),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP3_26_24, RX3_D_IRDA_RX_D, SEL_SCIF3_3),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP3_26_24, SDA3_B, SEL_I2C3_1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP3_26_24, SDA2_C, SEL_I2C2_2),
|
||||
PINMUX_IPSR_MSEL(IP3_26_24, RX3_D_IRDA_RX_D, SEL_SCIF3_3),
|
||||
PINMUX_IPSR_MSEL(IP3_26_24, SDA3_B, SEL_I2C3_1),
|
||||
PINMUX_IPSR_MSEL(IP3_26_24, SDA2_C, SEL_I2C2_2),
|
||||
PINMUX_IPSR_DATA(IP3_26_24, DACK0_B),
|
||||
PINMUX_IPSR_DATA(IP3_26_24, DRACK0_B),
|
||||
PINMUX_IPSR_DATA(IP3_27, DU0_EXHSYNC_DU0_HSYNC),
|
||||
|
|
@ -881,34 +881,34 @@ static const u16 pinmux_data[] = {
|
|||
PINMUX_IPSR_DATA(IP3_31_29, QCPV_QDE),
|
||||
PINMUX_IPSR_DATA(IP3_31_29, CAN1_TX),
|
||||
PINMUX_IPSR_DATA(IP3_31_29, TX2_C),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP3_31_29, SCL2_C, SEL_I2C2_2),
|
||||
PINMUX_IPSR_MSEL(IP3_31_29, SCL2_C, SEL_I2C2_2),
|
||||
PINMUX_IPSR_DATA(IP3_31_29, REMOCON),
|
||||
|
||||
PINMUX_IPSR_DATA(IP4_1_0, DU0_DISP),
|
||||
PINMUX_IPSR_DATA(IP4_1_0, QPOLA),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP4_1_0, CAN_CLK_C, SEL_CANCLK_2),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP4_1_0, SCK2_C, SEL_SCIF2_2),
|
||||
PINMUX_IPSR_MSEL(IP4_1_0, CAN_CLK_C, SEL_CANCLK_2),
|
||||
PINMUX_IPSR_MSEL(IP4_1_0, SCK2_C, SEL_SCIF2_2),
|
||||
PINMUX_IPSR_DATA(IP4_4_2, DU0_CDE),
|
||||
PINMUX_IPSR_DATA(IP4_4_2, QPOLB),
|
||||
PINMUX_IPSR_DATA(IP4_4_2, CAN1_RX),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP4_4_2, RX2_C, SEL_SCIF2_2),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP4_4_2, DREQ0_B, SEL_EXBUS0_1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SSI_SCK78_B, SEL_SSI7_1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SCK0_B, SEL_SCIF0_1),
|
||||
PINMUX_IPSR_MSEL(IP4_4_2, RX2_C, SEL_SCIF2_2),
|
||||
PINMUX_IPSR_MSEL(IP4_4_2, DREQ0_B, SEL_EXBUS0_1),
|
||||
PINMUX_IPSR_MSEL(IP4_4_2, SSI_SCK78_B, SEL_SSI7_1),
|
||||
PINMUX_IPSR_MSEL(IP4_4_2, SCK0_B, SEL_SCIF0_1),
|
||||
PINMUX_IPSR_DATA(IP4_7_5, DU1_DR0),
|
||||
PINMUX_IPSR_DATA(IP4_7_5, VI2_DATA0_VI2_B0),
|
||||
PINMUX_IPSR_DATA(IP4_7_5, PWM6),
|
||||
PINMUX_IPSR_DATA(IP4_7_5, SD3_CLK),
|
||||
PINMUX_IPSR_DATA(IP4_7_5, TX3_E_IRDA_TX_E),
|
||||
PINMUX_IPSR_DATA(IP4_7_5, AUDCK),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP4_7_5, PWMFSW0_B, SEL_PWMFSW_1),
|
||||
PINMUX_IPSR_MSEL(IP4_7_5, PWMFSW0_B, SEL_PWMFSW_1),
|
||||
PINMUX_IPSR_DATA(IP4_10_8, DU1_DR1),
|
||||
PINMUX_IPSR_DATA(IP4_10_8, VI2_DATA1_VI2_B1),
|
||||
PINMUX_IPSR_DATA(IP4_10_8, PWM0),
|
||||
PINMUX_IPSR_DATA(IP4_10_8, SD3_CMD),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP4_10_8, RX3_E_IRDA_RX_E, SEL_SCIF3_4),
|
||||
PINMUX_IPSR_MSEL(IP4_10_8, RX3_E_IRDA_RX_E, SEL_SCIF3_4),
|
||||
PINMUX_IPSR_DATA(IP4_10_8, AUDSYNC),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP4_10_8, CTS0_D, SEL_SCIF0_3),
|
||||
PINMUX_IPSR_MSEL(IP4_10_8, CTS0_D, SEL_SCIF0_3),
|
||||
PINMUX_IPSR_DATA(IP4_11, DU1_DR2),
|
||||
PINMUX_IPSR_DATA(IP4_11, VI2_G0),
|
||||
PINMUX_IPSR_DATA(IP4_12, DU1_DR3),
|
||||
|
|
@ -923,18 +923,18 @@ static const u16 pinmux_data[] = {
|
|||
PINMUX_IPSR_DATA(IP4_16, VI2_G5),
|
||||
PINMUX_IPSR_DATA(IP4_19_17, DU1_DG0),
|
||||
PINMUX_IPSR_DATA(IP4_19_17, VI2_DATA2_VI2_B2),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP4_19_17, SCL1_B, SEL_I2C1_1),
|
||||
PINMUX_IPSR_MSEL(IP4_19_17, SCL1_B, SEL_I2C1_1),
|
||||
PINMUX_IPSR_DATA(IP4_19_17, SD3_DAT2),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP4_19_17, SCK3_E, SEL_SCIF3_4),
|
||||
PINMUX_IPSR_MSEL(IP4_19_17, SCK3_E, SEL_SCIF3_4),
|
||||
PINMUX_IPSR_DATA(IP4_19_17, AUDATA6),
|
||||
PINMUX_IPSR_DATA(IP4_19_17, TX0_D),
|
||||
PINMUX_IPSR_DATA(IP4_22_20, DU1_DG1),
|
||||
PINMUX_IPSR_DATA(IP4_22_20, VI2_DATA3_VI2_B3),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP4_22_20, SDA1_B, SEL_I2C1_1),
|
||||
PINMUX_IPSR_MSEL(IP4_22_20, SDA1_B, SEL_I2C1_1),
|
||||
PINMUX_IPSR_DATA(IP4_22_20, SD3_DAT3),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP4_22_20, SCK5, SEL_SCIF5_0),
|
||||
PINMUX_IPSR_MSEL(IP4_22_20, SCK5, SEL_SCIF5_0),
|
||||
PINMUX_IPSR_DATA(IP4_22_20, AUDATA7),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP4_22_20, RX0_D, SEL_SCIF0_3),
|
||||
PINMUX_IPSR_MSEL(IP4_22_20, RX0_D, SEL_SCIF0_3),
|
||||
PINMUX_IPSR_DATA(IP4_23, DU1_DG2),
|
||||
PINMUX_IPSR_DATA(IP4_23, VI2_G6),
|
||||
PINMUX_IPSR_DATA(IP4_24, DU1_DG3),
|
||||
|
|
@ -949,17 +949,17 @@ static const u16 pinmux_data[] = {
|
|||
PINMUX_IPSR_DATA(IP4_28, VI2_R3),
|
||||
PINMUX_IPSR_DATA(IP4_31_29, DU1_DB0),
|
||||
PINMUX_IPSR_DATA(IP4_31_29, VI2_DATA4_VI2_B4),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP4_31_29, SCL2_B, SEL_I2C2_1),
|
||||
PINMUX_IPSR_MSEL(IP4_31_29, SCL2_B, SEL_I2C2_1),
|
||||
PINMUX_IPSR_DATA(IP4_31_29, SD3_DAT0),
|
||||
PINMUX_IPSR_DATA(IP4_31_29, TX5),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP4_31_29, SCK0_D, SEL_SCIF0_3),
|
||||
PINMUX_IPSR_MSEL(IP4_31_29, SCK0_D, SEL_SCIF0_3),
|
||||
|
||||
PINMUX_IPSR_DATA(IP5_2_0, DU1_DB1),
|
||||
PINMUX_IPSR_DATA(IP5_2_0, VI2_DATA5_VI2_B5),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP5_2_0, SDA2_B, SEL_I2C2_1),
|
||||
PINMUX_IPSR_MSEL(IP5_2_0, SDA2_B, SEL_I2C2_1),
|
||||
PINMUX_IPSR_DATA(IP5_2_0, SD3_DAT1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP5_2_0, RX5, SEL_SCIF5_0),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP5_2_0, RTS0_D_TANS_D, SEL_SCIF0_3),
|
||||
PINMUX_IPSR_MSEL(IP5_2_0, RX5, SEL_SCIF5_0),
|
||||
PINMUX_IPSR_MSEL(IP5_2_0, RTS0_D_TANS_D, SEL_SCIF0_3),
|
||||
PINMUX_IPSR_DATA(IP5_3, DU1_DB2),
|
||||
PINMUX_IPSR_DATA(IP5_3, VI2_R4),
|
||||
PINMUX_IPSR_DATA(IP5_4, DU1_DB3),
|
||||
|
|
@ -969,16 +969,16 @@ static const u16 pinmux_data[] = {
|
|||
PINMUX_IPSR_DATA(IP5_6, DU1_DB5),
|
||||
PINMUX_IPSR_DATA(IP5_6, VI2_R7),
|
||||
PINMUX_IPSR_DATA(IP5_7, DU1_DB6),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP5_7, SCL2_D, SEL_I2C2_3),
|
||||
PINMUX_IPSR_MSEL(IP5_7, SCL2_D, SEL_I2C2_3),
|
||||
PINMUX_IPSR_DATA(IP5_8, DU1_DB7),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP5_8, SDA2_D, SEL_I2C2_3),
|
||||
PINMUX_IPSR_MSEL(IP5_8, SDA2_D, SEL_I2C2_3),
|
||||
PINMUX_IPSR_DATA(IP5_10_9, DU1_DOTCLKIN),
|
||||
PINMUX_IPSR_DATA(IP5_10_9, VI2_CLKENB),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP5_10_9, HSPI_CS1, SEL_HSPI1_0),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP5_10_9, SCL1_D, SEL_I2C1_3),
|
||||
PINMUX_IPSR_MSEL(IP5_10_9, HSPI_CS1, SEL_HSPI1_0),
|
||||
PINMUX_IPSR_MSEL(IP5_10_9, SCL1_D, SEL_I2C1_3),
|
||||
PINMUX_IPSR_DATA(IP5_12_11, DU1_DOTCLKOUT),
|
||||
PINMUX_IPSR_DATA(IP5_12_11, VI2_FIELD),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP5_12_11, SDA1_D, SEL_I2C1_3),
|
||||
PINMUX_IPSR_MSEL(IP5_12_11, SDA1_D, SEL_I2C1_3),
|
||||
PINMUX_IPSR_DATA(IP5_14_13, DU1_EXHSYNC_DU1_HSYNC),
|
||||
PINMUX_IPSR_DATA(IP5_14_13, VI2_HSYNC),
|
||||
PINMUX_IPSR_DATA(IP5_14_13, VI3_HSYNC),
|
||||
|
|
@ -995,26 +995,26 @@ static const u16 pinmux_data[] = {
|
|||
PINMUX_IPSR_DATA(IP5_20_17, AUDIO_CLKC),
|
||||
PINMUX_IPSR_DATA(IP5_20_17, TX2_D),
|
||||
PINMUX_IPSR_DATA(IP5_20_17, SPEEDIN),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP5_20_17, GPS_SIGN_D, SEL_GPS_3),
|
||||
PINMUX_IPSR_MSEL(IP5_20_17, GPS_SIGN_D, SEL_GPS_3),
|
||||
PINMUX_IPSR_DATA(IP5_23_21, DU1_DISP),
|
||||
PINMUX_IPSR_DATA(IP5_23_21, VI2_DATA6_VI2_B6),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP5_23_21, TCLK0, SEL_TMU0_0),
|
||||
PINMUX_IPSR_MSEL(IP5_23_21, TCLK0, SEL_TMU0_0),
|
||||
PINMUX_IPSR_DATA(IP5_23_21, QSTVA_B_QVS_B),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP5_23_21, HSPI_CLK1, SEL_HSPI1_0),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP5_23_21, SCK2_D, SEL_SCIF2_3),
|
||||
PINMUX_IPSR_MSEL(IP5_23_21, HSPI_CLK1, SEL_HSPI1_0),
|
||||
PINMUX_IPSR_MSEL(IP5_23_21, SCK2_D, SEL_SCIF2_3),
|
||||
PINMUX_IPSR_DATA(IP5_23_21, AUDIO_CLKOUT_B),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP5_23_21, GPS_MAG_D, SEL_GPS_3),
|
||||
PINMUX_IPSR_MSEL(IP5_23_21, GPS_MAG_D, SEL_GPS_3),
|
||||
PINMUX_IPSR_DATA(IP5_27_24, DU1_CDE),
|
||||
PINMUX_IPSR_DATA(IP5_27_24, VI2_DATA7_VI2_B7),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP5_27_24, RX3_B_IRDA_RX_B, SEL_SCIF3_1),
|
||||
PINMUX_IPSR_MSEL(IP5_27_24, RX3_B_IRDA_RX_B, SEL_SCIF3_1),
|
||||
PINMUX_IPSR_DATA(IP5_27_24, SD3_WP),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP5_27_24, HSPI_RX1, SEL_HSPI1_0),
|
||||
PINMUX_IPSR_MSEL(IP5_27_24, HSPI_RX1, SEL_HSPI1_0),
|
||||
PINMUX_IPSR_DATA(IP5_27_24, VI1_FIELD),
|
||||
PINMUX_IPSR_DATA(IP5_27_24, VI3_FIELD),
|
||||
PINMUX_IPSR_DATA(IP5_27_24, AUDIO_CLKOUT),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP5_27_24, RX2_D, SEL_SCIF2_3),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP5_27_24, GPS_CLK_C, SEL_GPS_2),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP5_27_24, GPS_CLK_D, SEL_GPS_3),
|
||||
PINMUX_IPSR_MSEL(IP5_27_24, RX2_D, SEL_SCIF2_3),
|
||||
PINMUX_IPSR_MSEL(IP5_27_24, GPS_CLK_C, SEL_GPS_2),
|
||||
PINMUX_IPSR_MSEL(IP5_27_24, GPS_CLK_D, SEL_GPS_3),
|
||||
PINMUX_IPSR_DATA(IP5_28, AUDIO_CLKA),
|
||||
PINMUX_IPSR_DATA(IP5_28, CAN_TXCLK),
|
||||
PINMUX_IPSR_DATA(IP5_30_29, AUDIO_CLKB),
|
||||
|
|
@ -1039,82 +1039,82 @@ static const u16 pinmux_data[] = {
|
|||
PINMUX_IPSR_DATA(IP6_11_9, SSI_SCK34),
|
||||
PINMUX_IPSR_DATA(IP6_11_9, CAN_DEBUGOUT6),
|
||||
PINMUX_IPSR_DATA(IP6_11_9, CAN0_TX_B),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP6_11_9, IERX, SEL_IE_0),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP6_11_9, SSI_SCK9_C, SEL_SSI9_2),
|
||||
PINMUX_IPSR_MSEL(IP6_11_9, IERX, SEL_IE_0),
|
||||
PINMUX_IPSR_MSEL(IP6_11_9, SSI_SCK9_C, SEL_SSI9_2),
|
||||
PINMUX_IPSR_DATA(IP6_14_12, SSI_WS34),
|
||||
PINMUX_IPSR_DATA(IP6_14_12, CAN_DEBUGOUT7),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP6_14_12, CAN0_RX_B, SEL_CAN0_1),
|
||||
PINMUX_IPSR_MSEL(IP6_14_12, CAN0_RX_B, SEL_CAN0_1),
|
||||
PINMUX_IPSR_DATA(IP6_14_12, IETX),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP6_14_12, SSI_WS9_C, SEL_SSI9_2),
|
||||
PINMUX_IPSR_MSEL(IP6_14_12, SSI_WS9_C, SEL_SSI9_2),
|
||||
PINMUX_IPSR_DATA(IP6_17_15, SSI_SDATA3),
|
||||
PINMUX_IPSR_DATA(IP6_17_15, PWM0_C),
|
||||
PINMUX_IPSR_DATA(IP6_17_15, CAN_DEBUGOUT8),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP6_17_15, CAN_CLK_B, SEL_CANCLK_1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP6_17_15, IECLK, SEL_IE_0),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP6_17_15, SCIF_CLK_B, SEL_SCIF_1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP6_17_15, TCLK0_B, SEL_TMU0_1),
|
||||
PINMUX_IPSR_MSEL(IP6_17_15, CAN_CLK_B, SEL_CANCLK_1),
|
||||
PINMUX_IPSR_MSEL(IP6_17_15, IECLK, SEL_IE_0),
|
||||
PINMUX_IPSR_MSEL(IP6_17_15, SCIF_CLK_B, SEL_SCIF_1),
|
||||
PINMUX_IPSR_MSEL(IP6_17_15, TCLK0_B, SEL_TMU0_1),
|
||||
PINMUX_IPSR_DATA(IP6_19_18, SSI_SDATA4),
|
||||
PINMUX_IPSR_DATA(IP6_19_18, CAN_DEBUGOUT9),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP6_19_18, SSI_SDATA9_C, SEL_SSI9_2),
|
||||
PINMUX_IPSR_MSEL(IP6_19_18, SSI_SDATA9_C, SEL_SSI9_2),
|
||||
PINMUX_IPSR_DATA(IP6_22_20, SSI_SCK5),
|
||||
PINMUX_IPSR_DATA(IP6_22_20, ADICLK),
|
||||
PINMUX_IPSR_DATA(IP6_22_20, CAN_DEBUGOUT10),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCK3, SEL_SCIF3_0),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP6_22_20, TCLK0_D, SEL_TMU0_3),
|
||||
PINMUX_IPSR_MSEL(IP6_22_20, SCK3, SEL_SCIF3_0),
|
||||
PINMUX_IPSR_MSEL(IP6_22_20, TCLK0_D, SEL_TMU0_3),
|
||||
PINMUX_IPSR_DATA(IP6_24_23, SSI_WS5),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP6_24_23, ADICS_SAMP, SEL_ADI_0),
|
||||
PINMUX_IPSR_MSEL(IP6_24_23, ADICS_SAMP, SEL_ADI_0),
|
||||
PINMUX_IPSR_DATA(IP6_24_23, CAN_DEBUGOUT11),
|
||||
PINMUX_IPSR_DATA(IP6_24_23, TX3_IRDA_TX),
|
||||
PINMUX_IPSR_DATA(IP6_26_25, SSI_SDATA5),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP6_26_25, ADIDATA, SEL_ADI_0),
|
||||
PINMUX_IPSR_MSEL(IP6_26_25, ADIDATA, SEL_ADI_0),
|
||||
PINMUX_IPSR_DATA(IP6_26_25, CAN_DEBUGOUT12),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP6_26_25, RX3_IRDA_RX, SEL_SCIF3_0),
|
||||
PINMUX_IPSR_MSEL(IP6_26_25, RX3_IRDA_RX, SEL_SCIF3_0),
|
||||
PINMUX_IPSR_DATA(IP6_30_29, SSI_SCK6),
|
||||
PINMUX_IPSR_DATA(IP6_30_29, ADICHS0),
|
||||
PINMUX_IPSR_DATA(IP6_30_29, CAN0_TX),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP6_30_29, IERX_B, SEL_IE_1),
|
||||
PINMUX_IPSR_MSEL(IP6_30_29, IERX_B, SEL_IE_1),
|
||||
|
||||
PINMUX_IPSR_DATA(IP7_1_0, SSI_WS6),
|
||||
PINMUX_IPSR_DATA(IP7_1_0, ADICHS1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP7_1_0, CAN0_RX, SEL_CAN0_0),
|
||||
PINMUX_IPSR_MSEL(IP7_1_0, CAN0_RX, SEL_CAN0_0),
|
||||
PINMUX_IPSR_DATA(IP7_1_0, IETX_B),
|
||||
PINMUX_IPSR_DATA(IP7_3_2, SSI_SDATA6),
|
||||
PINMUX_IPSR_DATA(IP7_3_2, ADICHS2),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP7_3_2, CAN_CLK, SEL_CANCLK_0),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP7_3_2, IECLK_B, SEL_IE_1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP7_6_4, SSI_SCK78, SEL_SSI7_0),
|
||||
PINMUX_IPSR_MSEL(IP7_3_2, CAN_CLK, SEL_CANCLK_0),
|
||||
PINMUX_IPSR_MSEL(IP7_3_2, IECLK_B, SEL_IE_1),
|
||||
PINMUX_IPSR_MSEL(IP7_6_4, SSI_SCK78, SEL_SSI7_0),
|
||||
PINMUX_IPSR_DATA(IP7_6_4, CAN_DEBUGOUT13),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP7_6_4, IRQ0_B, SEL_INT0_1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP7_6_4, SSI_SCK9_B, SEL_SSI9_1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP7_6_4, HSPI_CLK1_C, SEL_HSPI1_2),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP7_9_7, SSI_WS78, SEL_SSI7_0),
|
||||
PINMUX_IPSR_MSEL(IP7_6_4, IRQ0_B, SEL_INT0_1),
|
||||
PINMUX_IPSR_MSEL(IP7_6_4, SSI_SCK9_B, SEL_SSI9_1),
|
||||
PINMUX_IPSR_MSEL(IP7_6_4, HSPI_CLK1_C, SEL_HSPI1_2),
|
||||
PINMUX_IPSR_MSEL(IP7_9_7, SSI_WS78, SEL_SSI7_0),
|
||||
PINMUX_IPSR_DATA(IP7_9_7, CAN_DEBUGOUT14),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP7_9_7, IRQ1_B, SEL_INT1_1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP7_9_7, SSI_WS9_B, SEL_SSI9_1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP7_9_7, HSPI_CS1_C, SEL_HSPI1_2),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP7_12_10, SSI_SDATA7, SEL_SSI7_0),
|
||||
PINMUX_IPSR_MSEL(IP7_9_7, IRQ1_B, SEL_INT1_1),
|
||||
PINMUX_IPSR_MSEL(IP7_9_7, SSI_WS9_B, SEL_SSI9_1),
|
||||
PINMUX_IPSR_MSEL(IP7_9_7, HSPI_CS1_C, SEL_HSPI1_2),
|
||||
PINMUX_IPSR_MSEL(IP7_12_10, SSI_SDATA7, SEL_SSI7_0),
|
||||
PINMUX_IPSR_DATA(IP7_12_10, CAN_DEBUGOUT15),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP7_12_10, IRQ2_B, SEL_INT2_1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP7_12_10, TCLK1_C, SEL_TMU1_2),
|
||||
PINMUX_IPSR_MSEL(IP7_12_10, IRQ2_B, SEL_INT2_1),
|
||||
PINMUX_IPSR_MSEL(IP7_12_10, TCLK1_C, SEL_TMU1_2),
|
||||
PINMUX_IPSR_DATA(IP7_12_10, HSPI_TX1_C),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP7_14_13, SSI_SDATA8, SEL_SSI8_0),
|
||||
PINMUX_IPSR_MSEL(IP7_14_13, SSI_SDATA8, SEL_SSI8_0),
|
||||
PINMUX_IPSR_DATA(IP7_14_13, VSP),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP7_14_13, IRQ3_B, SEL_INT3_1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP7_14_13, HSPI_RX1_C, SEL_HSPI1_2),
|
||||
PINMUX_IPSR_MSEL(IP7_14_13, IRQ3_B, SEL_INT3_1),
|
||||
PINMUX_IPSR_MSEL(IP7_14_13, HSPI_RX1_C, SEL_HSPI1_2),
|
||||
PINMUX_IPSR_DATA(IP7_16_15, SD0_CLK),
|
||||
PINMUX_IPSR_DATA(IP7_16_15, ATACS01),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP7_16_15, SCK1_B, SEL_SCIF1_1),
|
||||
PINMUX_IPSR_MSEL(IP7_16_15, SCK1_B, SEL_SCIF1_1),
|
||||
PINMUX_IPSR_DATA(IP7_18_17, SD0_CMD),
|
||||
PINMUX_IPSR_DATA(IP7_18_17, ATACS11),
|
||||
PINMUX_IPSR_DATA(IP7_18_17, TX1_B),
|
||||
PINMUX_IPSR_DATA(IP7_18_17, CC5_TDO),
|
||||
PINMUX_IPSR_DATA(IP7_20_19, SD0_DAT0),
|
||||
PINMUX_IPSR_DATA(IP7_20_19, ATADIR1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP7_20_19, RX1_B, SEL_SCIF1_1),
|
||||
PINMUX_IPSR_MSEL(IP7_20_19, RX1_B, SEL_SCIF1_1),
|
||||
PINMUX_IPSR_DATA(IP7_20_19, CC5_TRST),
|
||||
PINMUX_IPSR_DATA(IP7_22_21, SD0_DAT1),
|
||||
PINMUX_IPSR_DATA(IP7_22_21, ATAG1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP7_22_21, SCK2_B, SEL_SCIF2_1),
|
||||
PINMUX_IPSR_MSEL(IP7_22_21, SCK2_B, SEL_SCIF2_1),
|
||||
PINMUX_IPSR_DATA(IP7_22_21, CC5_TMS),
|
||||
PINMUX_IPSR_DATA(IP7_24_23, SD0_DAT2),
|
||||
PINMUX_IPSR_DATA(IP7_24_23, ATARD1),
|
||||
|
|
@ -1122,17 +1122,17 @@ static const u16 pinmux_data[] = {
|
|||
PINMUX_IPSR_DATA(IP7_24_23, CC5_TCK),
|
||||
PINMUX_IPSR_DATA(IP7_26_25, SD0_DAT3),
|
||||
PINMUX_IPSR_DATA(IP7_26_25, ATAWR1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP7_26_25, RX2_B, SEL_SCIF2_1),
|
||||
PINMUX_IPSR_MSEL(IP7_26_25, RX2_B, SEL_SCIF2_1),
|
||||
PINMUX_IPSR_DATA(IP7_26_25, CC5_TDI),
|
||||
PINMUX_IPSR_DATA(IP7_28_27, SD0_CD),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP7_28_27, DREQ2, SEL_EXBUS2_0),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP7_28_27, RTS1_B_TANS_B, SEL_SCIF1_1),
|
||||
PINMUX_IPSR_MSEL(IP7_28_27, DREQ2, SEL_EXBUS2_0),
|
||||
PINMUX_IPSR_MSEL(IP7_28_27, RTS1_B_TANS_B, SEL_SCIF1_1),
|
||||
PINMUX_IPSR_DATA(IP7_30_29, SD0_WP),
|
||||
PINMUX_IPSR_DATA(IP7_30_29, DACK2),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP7_30_29, CTS1_B, SEL_SCIF1_1),
|
||||
PINMUX_IPSR_MSEL(IP7_30_29, CTS1_B, SEL_SCIF1_1),
|
||||
|
||||
PINMUX_IPSR_DATA(IP8_3_0, HSPI_CLK0),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP8_3_0, CTS0, SEL_SCIF0_0),
|
||||
PINMUX_IPSR_MSEL(IP8_3_0, CTS0, SEL_SCIF0_0),
|
||||
PINMUX_IPSR_DATA(IP8_3_0, USB_OVC0),
|
||||
PINMUX_IPSR_DATA(IP8_3_0, AD_CLK),
|
||||
PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE4),
|
||||
|
|
@ -1141,7 +1141,7 @@ static const u16 pinmux_data[] = {
|
|||
PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE28),
|
||||
PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE36),
|
||||
PINMUX_IPSR_DATA(IP8_7_4, HSPI_CS0),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP8_7_4, RTS0_TANS, SEL_SCIF0_0),
|
||||
PINMUX_IPSR_MSEL(IP8_7_4, RTS0_TANS, SEL_SCIF0_0),
|
||||
PINMUX_IPSR_DATA(IP8_7_4, USB_OVC1),
|
||||
PINMUX_IPSR_DATA(IP8_7_4, AD_DI),
|
||||
PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE5),
|
||||
|
|
@ -1159,7 +1159,7 @@ static const u16 pinmux_data[] = {
|
|||
PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE30),
|
||||
PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE38),
|
||||
PINMUX_IPSR_DATA(IP8_15_12, HSPI_RX0),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP8_15_12, RX0, SEL_SCIF0_0),
|
||||
PINMUX_IPSR_MSEL(IP8_15_12, RX0, SEL_SCIF0_0),
|
||||
PINMUX_IPSR_DATA(IP8_15_12, CAN_STEP0),
|
||||
PINMUX_IPSR_DATA(IP8_15_12, AD_NCS),
|
||||
PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE7),
|
||||
|
|
@ -1181,25 +1181,25 @@ static const u16 pinmux_data[] = {
|
|||
PINMUX_IPSR_DATA(IP8_22_21, HTX1_B),
|
||||
PINMUX_IPSR_DATA(IP8_22_21, MT1_SYNC),
|
||||
PINMUX_IPSR_DATA(IP8_24_23, VI0_FIELD),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP8_24_23, RX1_C, SEL_SCIF1_2),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP8_24_23, HRX1_B, SEL_HSCIF1_1),
|
||||
PINMUX_IPSR_MSEL(IP8_24_23, RX1_C, SEL_SCIF1_2),
|
||||
PINMUX_IPSR_MSEL(IP8_24_23, HRX1_B, SEL_HSCIF1_1),
|
||||
PINMUX_IPSR_DATA(IP8_27_25, VI0_HSYNC),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP8_27_25, VI0_DATA0_B_VI0_B0_B, SEL_VI0_1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP8_27_25, CTS1_C, SEL_SCIF1_2),
|
||||
PINMUX_IPSR_MSEL(IP8_27_25, VI0_DATA0_B_VI0_B0_B, SEL_VI0_1),
|
||||
PINMUX_IPSR_MSEL(IP8_27_25, CTS1_C, SEL_SCIF1_2),
|
||||
PINMUX_IPSR_DATA(IP8_27_25, TX4_D),
|
||||
PINMUX_IPSR_DATA(IP8_27_25, MMC1_CMD),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP8_27_25, HSCK1_B, SEL_HSCIF1_1),
|
||||
PINMUX_IPSR_MSEL(IP8_27_25, HSCK1_B, SEL_HSCIF1_1),
|
||||
PINMUX_IPSR_DATA(IP8_30_28, VI0_VSYNC),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP8_30_28, VI0_DATA1_B_VI0_B1_B, SEL_VI0_1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP8_30_28, RTS1_C_TANS_C, SEL_SCIF1_2),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP8_30_28, RX4_D, SEL_SCIF4_3),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP8_30_28, PWMFSW0_C, SEL_PWMFSW_2),
|
||||
PINMUX_IPSR_MSEL(IP8_30_28, VI0_DATA1_B_VI0_B1_B, SEL_VI0_1),
|
||||
PINMUX_IPSR_MSEL(IP8_30_28, RTS1_C_TANS_C, SEL_SCIF1_2),
|
||||
PINMUX_IPSR_MSEL(IP8_30_28, RX4_D, SEL_SCIF4_3),
|
||||
PINMUX_IPSR_MSEL(IP8_30_28, PWMFSW0_C, SEL_PWMFSW_2),
|
||||
|
||||
PINMUX_IPSR_MODSEL_DATA(IP9_1_0, VI0_DATA0_VI0_B0, SEL_VI0_0),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP9_1_0, HRTS1_B, SEL_HSCIF1_1),
|
||||
PINMUX_IPSR_MSEL(IP9_1_0, VI0_DATA0_VI0_B0, SEL_VI0_0),
|
||||
PINMUX_IPSR_MSEL(IP9_1_0, HRTS1_B, SEL_HSCIF1_1),
|
||||
PINMUX_IPSR_DATA(IP9_1_0, MT1_VCXO),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP9_3_2, VI0_DATA1_VI0_B1, SEL_VI0_0),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP9_3_2, HCTS1_B, SEL_HSCIF1_1),
|
||||
PINMUX_IPSR_MSEL(IP9_3_2, VI0_DATA1_VI0_B1, SEL_VI0_0),
|
||||
PINMUX_IPSR_MSEL(IP9_3_2, HCTS1_B, SEL_HSCIF1_1),
|
||||
PINMUX_IPSR_DATA(IP9_3_2, MT1_PWM),
|
||||
PINMUX_IPSR_DATA(IP9_4, VI0_DATA2_VI0_B2),
|
||||
PINMUX_IPSR_DATA(IP9_4, MMC1_D0),
|
||||
|
|
@ -1216,12 +1216,12 @@ static const u16 pinmux_data[] = {
|
|||
PINMUX_IPSR_DATA(IP9_11_10, MMC1_D5),
|
||||
PINMUX_IPSR_DATA(IP9_11_10, ARM_TRACEDATA_1),
|
||||
PINMUX_IPSR_DATA(IP9_13_12, VI0_G0),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP9_13_12, SSI_SCK78_C, SEL_SSI7_2),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP9_13_12, IRQ0, SEL_INT0_0),
|
||||
PINMUX_IPSR_MSEL(IP9_13_12, SSI_SCK78_C, SEL_SSI7_2),
|
||||
PINMUX_IPSR_MSEL(IP9_13_12, IRQ0, SEL_INT0_0),
|
||||
PINMUX_IPSR_DATA(IP9_13_12, ARM_TRACEDATA_2),
|
||||
PINMUX_IPSR_DATA(IP9_15_14, VI0_G1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP9_15_14, SSI_WS78_C, SEL_SSI7_2),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP9_15_14, IRQ1, SEL_INT1_0),
|
||||
PINMUX_IPSR_MSEL(IP9_15_14, SSI_WS78_C, SEL_SSI7_2),
|
||||
PINMUX_IPSR_MSEL(IP9_15_14, IRQ1, SEL_INT1_0),
|
||||
PINMUX_IPSR_DATA(IP9_15_14, ARM_TRACEDATA_3),
|
||||
PINMUX_IPSR_DATA(IP9_18_16, VI0_G2),
|
||||
PINMUX_IPSR_DATA(IP9_18_16, ETH_TXD1),
|
||||
|
|
@ -1235,29 +1235,29 @@ static const u16 pinmux_data[] = {
|
|||
PINMUX_IPSR_DATA(IP9_21_19, TS_SDAT0),
|
||||
PINMUX_IPSR_DATA(IP9_23_22, VI0_G4),
|
||||
PINMUX_IPSR_DATA(IP9_23_22, ETH_TX_EN),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP9_23_22, SD2_DAT0_B, SEL_SD2_1),
|
||||
PINMUX_IPSR_MSEL(IP9_23_22, SD2_DAT0_B, SEL_SD2_1),
|
||||
PINMUX_IPSR_DATA(IP9_23_22, ARM_TRACEDATA_6),
|
||||
PINMUX_IPSR_DATA(IP9_25_24, VI0_G5),
|
||||
PINMUX_IPSR_DATA(IP9_25_24, ETH_RX_ER),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP9_25_24, SD2_DAT1_B, SEL_SD2_1),
|
||||
PINMUX_IPSR_MSEL(IP9_25_24, SD2_DAT1_B, SEL_SD2_1),
|
||||
PINMUX_IPSR_DATA(IP9_25_24, ARM_TRACEDATA_7),
|
||||
PINMUX_IPSR_DATA(IP9_27_26, VI0_G6),
|
||||
PINMUX_IPSR_DATA(IP9_27_26, ETH_RXD0),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP9_27_26, SD2_DAT2_B, SEL_SD2_1),
|
||||
PINMUX_IPSR_MSEL(IP9_27_26, SD2_DAT2_B, SEL_SD2_1),
|
||||
PINMUX_IPSR_DATA(IP9_27_26, ARM_TRACEDATA_8),
|
||||
PINMUX_IPSR_DATA(IP9_29_28, VI0_G7),
|
||||
PINMUX_IPSR_DATA(IP9_29_28, ETH_RXD1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP9_29_28, SD2_DAT3_B, SEL_SD2_1),
|
||||
PINMUX_IPSR_MSEL(IP9_29_28, SD2_DAT3_B, SEL_SD2_1),
|
||||
PINMUX_IPSR_DATA(IP9_29_28, ARM_TRACEDATA_9),
|
||||
|
||||
PINMUX_IPSR_DATA(IP10_2_0, VI0_R0),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SSI_SDATA7_C, SEL_SSI7_2),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SCK1_C, SEL_SCIF1_2),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP10_2_0, DREQ1_B, SEL_EXBUS1_0),
|
||||
PINMUX_IPSR_MSEL(IP10_2_0, SSI_SDATA7_C, SEL_SSI7_2),
|
||||
PINMUX_IPSR_MSEL(IP10_2_0, SCK1_C, SEL_SCIF1_2),
|
||||
PINMUX_IPSR_MSEL(IP10_2_0, DREQ1_B, SEL_EXBUS1_0),
|
||||
PINMUX_IPSR_DATA(IP10_2_0, ARM_TRACEDATA_10),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP10_2_0, DREQ0_C, SEL_EXBUS0_2),
|
||||
PINMUX_IPSR_MSEL(IP10_2_0, DREQ0_C, SEL_EXBUS0_2),
|
||||
PINMUX_IPSR_DATA(IP10_5_3, VI0_R1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP10_5_3, SSI_SDATA8_C, SEL_SSI8_2),
|
||||
PINMUX_IPSR_MSEL(IP10_5_3, SSI_SDATA8_C, SEL_SSI8_2),
|
||||
PINMUX_IPSR_DATA(IP10_5_3, DACK1_B),
|
||||
PINMUX_IPSR_DATA(IP10_5_3, ARM_TRACEDATA_11),
|
||||
PINMUX_IPSR_DATA(IP10_5_3, DACK0_C),
|
||||
|
|
@ -1265,74 +1265,74 @@ static const u16 pinmux_data[] = {
|
|||
PINMUX_IPSR_DATA(IP10_8_6, VI0_R2),
|
||||
PINMUX_IPSR_DATA(IP10_8_6, ETH_LINK),
|
||||
PINMUX_IPSR_DATA(IP10_8_6, SD2_CLK_B),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP10_8_6, IRQ2, SEL_INT2_0),
|
||||
PINMUX_IPSR_MSEL(IP10_8_6, IRQ2, SEL_INT2_0),
|
||||
PINMUX_IPSR_DATA(IP10_8_6, ARM_TRACEDATA_12),
|
||||
PINMUX_IPSR_DATA(IP10_11_9, VI0_R3),
|
||||
PINMUX_IPSR_DATA(IP10_11_9, ETH_MAGIC),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP10_11_9, SD2_CMD_B, SEL_SD2_1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP10_11_9, IRQ3, SEL_INT3_0),
|
||||
PINMUX_IPSR_MSEL(IP10_11_9, SD2_CMD_B, SEL_SD2_1),
|
||||
PINMUX_IPSR_MSEL(IP10_11_9, IRQ3, SEL_INT3_0),
|
||||
PINMUX_IPSR_DATA(IP10_11_9, ARM_TRACEDATA_13),
|
||||
PINMUX_IPSR_DATA(IP10_14_12, VI0_R4),
|
||||
PINMUX_IPSR_DATA(IP10_14_12, ETH_REFCLK),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP10_14_12, SD2_CD_B, SEL_SD2_1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP10_14_12, HSPI_CLK1_B, SEL_HSPI1_1),
|
||||
PINMUX_IPSR_MSEL(IP10_14_12, SD2_CD_B, SEL_SD2_1),
|
||||
PINMUX_IPSR_MSEL(IP10_14_12, HSPI_CLK1_B, SEL_HSPI1_1),
|
||||
PINMUX_IPSR_DATA(IP10_14_12, ARM_TRACEDATA_14),
|
||||
PINMUX_IPSR_DATA(IP10_14_12, MT1_CLK),
|
||||
PINMUX_IPSR_DATA(IP10_14_12, TS_SCK0),
|
||||
PINMUX_IPSR_DATA(IP10_17_15, VI0_R5),
|
||||
PINMUX_IPSR_DATA(IP10_17_15, ETH_TXD0),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP10_17_15, SD2_WP_B, SEL_SD2_1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP10_17_15, HSPI_CS1_B, SEL_HSPI1_1),
|
||||
PINMUX_IPSR_MSEL(IP10_17_15, SD2_WP_B, SEL_SD2_1),
|
||||
PINMUX_IPSR_MSEL(IP10_17_15, HSPI_CS1_B, SEL_HSPI1_1),
|
||||
PINMUX_IPSR_DATA(IP10_17_15, ARM_TRACEDATA_15),
|
||||
PINMUX_IPSR_DATA(IP10_17_15, MT1_D),
|
||||
PINMUX_IPSR_DATA(IP10_17_15, TS_SDEN0),
|
||||
PINMUX_IPSR_DATA(IP10_20_18, VI0_R6),
|
||||
PINMUX_IPSR_DATA(IP10_20_18, ETH_MDC),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP10_20_18, DREQ2_C, SEL_EXBUS2_2),
|
||||
PINMUX_IPSR_MSEL(IP10_20_18, DREQ2_C, SEL_EXBUS2_2),
|
||||
PINMUX_IPSR_DATA(IP10_20_18, HSPI_TX1_B),
|
||||
PINMUX_IPSR_DATA(IP10_20_18, TRACECLK),
|
||||
PINMUX_IPSR_DATA(IP10_20_18, MT1_BEN),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP10_20_18, PWMFSW0_D, SEL_PWMFSW_3),
|
||||
PINMUX_IPSR_MSEL(IP10_20_18, PWMFSW0_D, SEL_PWMFSW_3),
|
||||
PINMUX_IPSR_DATA(IP10_23_21, VI0_R7),
|
||||
PINMUX_IPSR_DATA(IP10_23_21, ETH_MDIO),
|
||||
PINMUX_IPSR_DATA(IP10_23_21, DACK2_C),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP10_23_21, HSPI_RX1_B, SEL_HSPI1_1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP10_23_21, SCIF_CLK_D, SEL_SCIF_3),
|
||||
PINMUX_IPSR_MSEL(IP10_23_21, HSPI_RX1_B, SEL_HSPI1_1),
|
||||
PINMUX_IPSR_MSEL(IP10_23_21, SCIF_CLK_D, SEL_SCIF_3),
|
||||
PINMUX_IPSR_DATA(IP10_23_21, TRACECTL),
|
||||
PINMUX_IPSR_DATA(IP10_23_21, MT1_PEN),
|
||||
PINMUX_IPSR_DATA(IP10_25_24, VI1_CLK),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP10_25_24, SIM_D, SEL_SIM_0),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP10_25_24, SDA3, SEL_I2C3_0),
|
||||
PINMUX_IPSR_MSEL(IP10_25_24, SIM_D, SEL_SIM_0),
|
||||
PINMUX_IPSR_MSEL(IP10_25_24, SDA3, SEL_I2C3_0),
|
||||
PINMUX_IPSR_DATA(IP10_28_26, VI1_HSYNC),
|
||||
PINMUX_IPSR_DATA(IP10_28_26, VI3_CLK),
|
||||
PINMUX_IPSR_DATA(IP10_28_26, SSI_SCK4),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP10_28_26, GPS_SIGN_C, SEL_GPS_2),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP10_28_26, PWMFSW0_E, SEL_PWMFSW_4),
|
||||
PINMUX_IPSR_MSEL(IP10_28_26, GPS_SIGN_C, SEL_GPS_2),
|
||||
PINMUX_IPSR_MSEL(IP10_28_26, PWMFSW0_E, SEL_PWMFSW_4),
|
||||
PINMUX_IPSR_DATA(IP10_31_29, VI1_VSYNC),
|
||||
PINMUX_IPSR_DATA(IP10_31_29, AUDIO_CLKOUT_C),
|
||||
PINMUX_IPSR_DATA(IP10_31_29, SSI_WS4),
|
||||
PINMUX_IPSR_DATA(IP10_31_29, SIM_CLK),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP10_31_29, GPS_MAG_C, SEL_GPS_2),
|
||||
PINMUX_IPSR_MSEL(IP10_31_29, GPS_MAG_C, SEL_GPS_2),
|
||||
PINMUX_IPSR_DATA(IP10_31_29, SPV_TRST),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP10_31_29, SCL3, SEL_I2C3_0),
|
||||
PINMUX_IPSR_MSEL(IP10_31_29, SCL3, SEL_I2C3_0),
|
||||
|
||||
PINMUX_IPSR_DATA(IP11_2_0, VI1_DATA0_VI1_B0),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SD2_DAT0, SEL_SD2_0),
|
||||
PINMUX_IPSR_MSEL(IP11_2_0, SD2_DAT0, SEL_SD2_0),
|
||||
PINMUX_IPSR_DATA(IP11_2_0, SIM_RST),
|
||||
PINMUX_IPSR_DATA(IP11_2_0, SPV_TCK),
|
||||
PINMUX_IPSR_DATA(IP11_2_0, ADICLK_B),
|
||||
PINMUX_IPSR_DATA(IP11_5_3, VI1_DATA1_VI1_B1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SD2_DAT1, SEL_SD2_0),
|
||||
PINMUX_IPSR_MSEL(IP11_5_3, SD2_DAT1, SEL_SD2_0),
|
||||
PINMUX_IPSR_DATA(IP11_5_3, MT0_CLK),
|
||||
PINMUX_IPSR_DATA(IP11_5_3, SPV_TMS),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP11_5_3, ADICS_B_SAMP_B, SEL_ADI_1),
|
||||
PINMUX_IPSR_MSEL(IP11_5_3, ADICS_B_SAMP_B, SEL_ADI_1),
|
||||
PINMUX_IPSR_DATA(IP11_8_6, VI1_DATA2_VI1_B2),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SD2_DAT2, SEL_SD2_0),
|
||||
PINMUX_IPSR_MSEL(IP11_8_6, SD2_DAT2, SEL_SD2_0),
|
||||
PINMUX_IPSR_DATA(IP11_8_6, MT0_D),
|
||||
PINMUX_IPSR_DATA(IP11_8_6, SPVTDI),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP11_8_6, ADIDATA_B, SEL_ADI_1),
|
||||
PINMUX_IPSR_MSEL(IP11_8_6, ADIDATA_B, SEL_ADI_1),
|
||||
PINMUX_IPSR_DATA(IP11_11_9, VI1_DATA3_VI1_B3),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP11_11_9, SD2_DAT3, SEL_SD2_0),
|
||||
PINMUX_IPSR_MSEL(IP11_11_9, SD2_DAT3, SEL_SD2_0),
|
||||
PINMUX_IPSR_DATA(IP11_11_9, MT0_BEN),
|
||||
PINMUX_IPSR_DATA(IP11_11_9, SPV_TDO),
|
||||
PINMUX_IPSR_DATA(IP11_11_9, ADICHS0_B),
|
||||
|
|
@ -1340,74 +1340,74 @@ static const u16 pinmux_data[] = {
|
|||
PINMUX_IPSR_DATA(IP11_14_12, SD2_CLK),
|
||||
PINMUX_IPSR_DATA(IP11_14_12, MT0_PEN),
|
||||
PINMUX_IPSR_DATA(IP11_14_12, SPA_TRST),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP11_14_12, HSPI_CLK1_D, SEL_HSPI1_3),
|
||||
PINMUX_IPSR_MSEL(IP11_14_12, HSPI_CLK1_D, SEL_HSPI1_3),
|
||||
PINMUX_IPSR_DATA(IP11_14_12, ADICHS1_B),
|
||||
PINMUX_IPSR_DATA(IP11_17_15, VI1_DATA5_VI1_B5),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP11_17_15, SD2_CMD, SEL_SD2_0),
|
||||
PINMUX_IPSR_MSEL(IP11_17_15, SD2_CMD, SEL_SD2_0),
|
||||
PINMUX_IPSR_DATA(IP11_17_15, MT0_SYNC),
|
||||
PINMUX_IPSR_DATA(IP11_17_15, SPA_TCK),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP11_17_15, HSPI_CS1_D, SEL_HSPI1_3),
|
||||
PINMUX_IPSR_MSEL(IP11_17_15, HSPI_CS1_D, SEL_HSPI1_3),
|
||||
PINMUX_IPSR_DATA(IP11_17_15, ADICHS2_B),
|
||||
PINMUX_IPSR_DATA(IP11_20_18, VI1_DATA6_VI1_B6),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP11_20_18, SD2_CD, SEL_SD2_0),
|
||||
PINMUX_IPSR_MSEL(IP11_20_18, SD2_CD, SEL_SD2_0),
|
||||
PINMUX_IPSR_DATA(IP11_20_18, MT0_VCXO),
|
||||
PINMUX_IPSR_DATA(IP11_20_18, SPA_TMS),
|
||||
PINMUX_IPSR_DATA(IP11_20_18, HSPI_TX1_D),
|
||||
PINMUX_IPSR_DATA(IP11_23_21, VI1_DATA7_VI1_B7),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP11_23_21, SD2_WP, SEL_SD2_0),
|
||||
PINMUX_IPSR_MSEL(IP11_23_21, SD2_WP, SEL_SD2_0),
|
||||
PINMUX_IPSR_DATA(IP11_23_21, MT0_PWM),
|
||||
PINMUX_IPSR_DATA(IP11_23_21, SPA_TDI),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP11_23_21, HSPI_RX1_D, SEL_HSPI1_3),
|
||||
PINMUX_IPSR_MSEL(IP11_23_21, HSPI_RX1_D, SEL_HSPI1_3),
|
||||
PINMUX_IPSR_DATA(IP11_26_24, VI1_G0),
|
||||
PINMUX_IPSR_DATA(IP11_26_24, VI3_DATA0),
|
||||
PINMUX_IPSR_DATA(IP11_26_24, TS_SCK1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP11_26_24, DREQ2_B, SEL_EXBUS2_1),
|
||||
PINMUX_IPSR_MSEL(IP11_26_24, DREQ2_B, SEL_EXBUS2_1),
|
||||
PINMUX_IPSR_DATA(IP11_26_24, TX2),
|
||||
PINMUX_IPSR_DATA(IP11_26_24, SPA_TDO),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP11_26_24, HCTS0_B, SEL_HSCIF0_1),
|
||||
PINMUX_IPSR_MSEL(IP11_26_24, HCTS0_B, SEL_HSCIF0_1),
|
||||
PINMUX_IPSR_DATA(IP11_29_27, VI1_G1),
|
||||
PINMUX_IPSR_DATA(IP11_29_27, VI3_DATA1),
|
||||
PINMUX_IPSR_DATA(IP11_29_27, SSI_SCK1),
|
||||
PINMUX_IPSR_DATA(IP11_29_27, TS_SDEN1),
|
||||
PINMUX_IPSR_DATA(IP11_29_27, DACK2_B),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP11_29_27, RX2, SEL_SCIF2_0),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP11_29_27, HRTS0_B, SEL_HSCIF0_1),
|
||||
PINMUX_IPSR_MSEL(IP11_29_27, RX2, SEL_SCIF2_0),
|
||||
PINMUX_IPSR_MSEL(IP11_29_27, HRTS0_B, SEL_HSCIF0_1),
|
||||
|
||||
PINMUX_IPSR_DATA(IP12_2_0, VI1_G2),
|
||||
PINMUX_IPSR_DATA(IP12_2_0, VI3_DATA2),
|
||||
PINMUX_IPSR_DATA(IP12_2_0, SSI_WS1),
|
||||
PINMUX_IPSR_DATA(IP12_2_0, TS_SPSYNC1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP12_2_0, SCK2, SEL_SCIF2_0),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP12_2_0, HSCK0_B, SEL_HSCIF0_1),
|
||||
PINMUX_IPSR_MSEL(IP12_2_0, SCK2, SEL_SCIF2_0),
|
||||
PINMUX_IPSR_MSEL(IP12_2_0, HSCK0_B, SEL_HSCIF0_1),
|
||||
PINMUX_IPSR_DATA(IP12_5_3, VI1_G3),
|
||||
PINMUX_IPSR_DATA(IP12_5_3, VI3_DATA3),
|
||||
PINMUX_IPSR_DATA(IP12_5_3, SSI_SCK2),
|
||||
PINMUX_IPSR_DATA(IP12_5_3, TS_SDAT1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP12_5_3, SCL1_C, SEL_I2C1_2),
|
||||
PINMUX_IPSR_MSEL(IP12_5_3, SCL1_C, SEL_I2C1_2),
|
||||
PINMUX_IPSR_DATA(IP12_5_3, HTX0_B),
|
||||
PINMUX_IPSR_DATA(IP12_8_6, VI1_G4),
|
||||
PINMUX_IPSR_DATA(IP12_8_6, VI3_DATA4),
|
||||
PINMUX_IPSR_DATA(IP12_8_6, SSI_WS2),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP12_8_6, SDA1_C, SEL_I2C1_2),
|
||||
PINMUX_IPSR_MSEL(IP12_8_6, SDA1_C, SEL_I2C1_2),
|
||||
PINMUX_IPSR_DATA(IP12_8_6, SIM_RST_B),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP12_8_6, HRX0_B, SEL_HSCIF0_1),
|
||||
PINMUX_IPSR_MSEL(IP12_8_6, HRX0_B, SEL_HSCIF0_1),
|
||||
PINMUX_IPSR_DATA(IP12_11_9, VI1_G5),
|
||||
PINMUX_IPSR_DATA(IP12_11_9, VI3_DATA5),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP12_11_9, GPS_CLK, SEL_GPS_0),
|
||||
PINMUX_IPSR_MSEL(IP12_11_9, GPS_CLK, SEL_GPS_0),
|
||||
PINMUX_IPSR_DATA(IP12_11_9, FSE),
|
||||
PINMUX_IPSR_DATA(IP12_11_9, TX4_B),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP12_11_9, SIM_D_B, SEL_SIM_1),
|
||||
PINMUX_IPSR_MSEL(IP12_11_9, SIM_D_B, SEL_SIM_1),
|
||||
PINMUX_IPSR_DATA(IP12_14_12, VI1_G6),
|
||||
PINMUX_IPSR_DATA(IP12_14_12, VI3_DATA6),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP12_14_12, GPS_SIGN, SEL_GPS_0),
|
||||
PINMUX_IPSR_MSEL(IP12_14_12, GPS_SIGN, SEL_GPS_0),
|
||||
PINMUX_IPSR_DATA(IP12_14_12, FRB),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP12_14_12, RX4_B, SEL_SCIF4_1),
|
||||
PINMUX_IPSR_MSEL(IP12_14_12, RX4_B, SEL_SCIF4_1),
|
||||
PINMUX_IPSR_DATA(IP12_14_12, SIM_CLK_B),
|
||||
PINMUX_IPSR_DATA(IP12_17_15, VI1_G7),
|
||||
PINMUX_IPSR_DATA(IP12_17_15, VI3_DATA7),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP12_17_15, GPS_MAG, SEL_GPS_0),
|
||||
PINMUX_IPSR_MSEL(IP12_17_15, GPS_MAG, SEL_GPS_0),
|
||||
PINMUX_IPSR_DATA(IP12_17_15, FCE),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP12_17_15, SCK4_B, SEL_SCIF4_1),
|
||||
PINMUX_IPSR_MSEL(IP12_17_15, SCK4_B, SEL_SCIF4_1),
|
||||
};
|
||||
|
||||
static const struct sh_pfc_pin pinmux_pins[] = {
|
||||
|
|
|
|||
Loading…
Reference in New Issue