drm/amd/display: Add double buffer machanism to ICSC
- Video playback shows tearing when adjusting brightness through radeon custom settings. - Now added double buffer mechanism to switch input CSC from register buffer ICSC and COMA - Improved tab alignment Signed-off-by: Xingyue Tao <xingyue.tao@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Xingyue Tao
Alex Deucher
parent
8d815b4635
commit
7608f8569d
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@ -108,6 +108,8 @@
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SRI(CM_DGAM_LUT_DATA, CM, id), \
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SRI(CM_CONTROL, CM, id), \
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SRI(CM_DGAM_CONTROL, CM, id), \
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SRI(CM_TEST_DEBUG_INDEX, CM, id), \
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SRI(CM_TEST_DEBUG_DATA, CM, id), \
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SRI(FORMAT_CONTROL, CNVC_CFG, id), \
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SRI(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \
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SRI(CURSOR0_CONTROL, CNVC_CUR, id), \
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@ -300,6 +302,7 @@
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TF_SF(CM0_CM_DGAM_LUT_INDEX, CM_DGAM_LUT_INDEX, mask_sh), \
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TF_SF(CM0_CM_DGAM_LUT_DATA, CM_DGAM_LUT_DATA, mask_sh), \
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TF_SF(CM0_CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, mask_sh), \
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TF_SF(CM0_CM_TEST_DEBUG_INDEX, CM_TEST_DEBUG_INDEX, mask_sh), \
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TF_SF(CNVC_CFG0_FORMAT_CONTROL, CNVC_BYPASS, mask_sh), \
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TF2_SF(CNVC_CFG0, FORMAT_CONTROL__ALPHA_EN, mask_sh), \
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TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_EXPANSION_MODE, mask_sh), \
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@ -1010,6 +1013,8 @@
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type CUR0_EXPANSION_MODE; \
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type CUR0_ENABLE; \
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type CM_BYPASS; \
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type CM_TEST_DEBUG_INDEX; \
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type CM_TEST_DEBUG_DATA_ID9_ICSC_MODE; \
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type FORMAT_CONTROL__ALPHA_EN; \
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type CUR0_COLOR0; \
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type CUR0_COLOR1; \
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@ -1255,6 +1260,8 @@ struct dcn_dpp_mask {
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uint32_t CM_IGAM_LUT_RW_CONTROL; \
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uint32_t CM_IGAM_LUT_RW_INDEX; \
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uint32_t CM_IGAM_LUT_SEQ_COLOR; \
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uint32_t CM_TEST_DEBUG_INDEX; \
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uint32_t CM_TEST_DEBUG_DATA; \
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uint32_t FORMAT_CONTROL; \
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uint32_t CNVC_SURFACE_PIXEL_FORMAT; \
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uint32_t CURSOR_CONTROL; \
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@ -1289,8 +1296,8 @@ struct dcn10_dpp {
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enum dcn10_input_csc_select {
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INPUT_CSC_SELECT_BYPASS = 0,
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INPUT_CSC_SELECT_ICSC,
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INPUT_CSC_SELECT_COMA
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INPUT_CSC_SELECT_ICSC = 1,
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INPUT_CSC_SELECT_COMA = 2
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};
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void dpp1_set_cursor_attributes(
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@ -267,6 +267,7 @@ void dpp1_cm_set_output_csc_default(
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BREAK_TO_DEBUGGER();
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return;
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}
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dpp1_cm_program_color_matrix(dpp, regval);
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REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode);
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}
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@ -330,6 +331,7 @@ void dpp1_cm_set_output_csc_adjustment(
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{
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struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
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uint32_t ocsc_mode = 4;
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dpp1_cm_program_color_matrix(dpp, regval);
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REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode);
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}
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@ -437,17 +439,18 @@ void dpp1_cm_program_regamma_lutb_settings(
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void dpp1_program_input_csc(
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struct dpp *dpp_base,
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enum dc_color_space color_space,
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enum dcn10_input_csc_select select,
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enum dcn10_input_csc_select input_select,
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const struct out_csc_color_matrix *tbl_entry)
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{
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struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
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int i;
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int arr_size = sizeof(dcn10_input_csc_matrix)/sizeof(struct dcn10_input_csc_matrix);
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const uint16_t *regval = NULL;
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uint32_t selection = 1;
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uint32_t cur_select = 0;
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enum dcn10_input_csc_select select;
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struct color_matrices_reg gam_regs;
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if (select == INPUT_CSC_SELECT_BYPASS) {
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if (input_select == INPUT_CSC_SELECT_BYPASS) {
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REG_SET(CM_ICSC_CONTROL, 0, CM_ICSC_MODE, 0);
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return;
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}
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@ -467,36 +470,45 @@ void dpp1_program_input_csc(
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regval = tbl_entry->regval;
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}
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if (select == INPUT_CSC_SELECT_COMA)
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selection = 2;
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REG_SET(CM_ICSC_CONTROL, 0,
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CM_ICSC_MODE, selection);
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/* determine which CSC matrix (icsc or coma) we are using
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* currently. select the alternate set to double buffer
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* the CSC update so CSC is updated on frame boundary
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*/
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REG_SET(CM_TEST_DEBUG_INDEX, 0,
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CM_TEST_DEBUG_INDEX, 9);
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REG_GET(CM_TEST_DEBUG_DATA,
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CM_TEST_DEBUG_DATA_ID9_ICSC_MODE, &cur_select);
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if (cur_select != INPUT_CSC_SELECT_ICSC)
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select = INPUT_CSC_SELECT_ICSC;
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else
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select = INPUT_CSC_SELECT_COMA;
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gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_ICSC_C11;
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gam_regs.masks.csc_c11 = dpp->tf_mask->CM_ICSC_C11;
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gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_ICSC_C12;
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gam_regs.masks.csc_c12 = dpp->tf_mask->CM_ICSC_C12;
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if (select == INPUT_CSC_SELECT_ICSC) {
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gam_regs.csc_c11_c12 = REG(CM_ICSC_C11_C12);
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gam_regs.csc_c33_c34 = REG(CM_ICSC_C33_C34);
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cm_helper_program_color_matrices(
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dpp->base.ctx,
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regval,
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&gam_regs);
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} else {
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gam_regs.csc_c11_c12 = REG(CM_COMA_C11_C12);
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gam_regs.csc_c33_c34 = REG(CM_COMA_C33_C34);
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}
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cm_helper_program_color_matrices(
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dpp->base.ctx,
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regval,
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&gam_regs);
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}
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REG_SET(CM_ICSC_CONTROL, 0,
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CM_ICSC_MODE, select);
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}
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//keep here for now, decide multi dce support later
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@ -319,12 +319,41 @@ static const struct dcn_dpp_registers tf_regs[] = {
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tf_regs(3),
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};
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/*
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*
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DCN1 CM debug status register definition
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register :ID9_CM_STATUS do
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implement_ref :cm
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map to: :cmdebugind, at: j
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width 32
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disclosure NEVER
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field :ID9_VUPDATE_CFG, [0], R
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field :ID9_IGAM_LUT_MODE, [2..1], R
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field :ID9_BNS_BYPASS, [3], R
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field :ID9_ICSC_MODE, [5..4], R
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field :ID9_DGAM_LUT_MODE, [8..6], R
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field :ID9_HDR_BYPASS, [9], R
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field :ID9_GAMUT_REMAP_MODE, [11..10], R
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field :ID9_RGAM_LUT_MODE, [14..12], R
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#1 free bit
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field :ID9_OCSC_MODE, [18..16], R
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field :ID9_DENORM_MODE, [21..19], R
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field :ID9_ROUND_TRUNC_MODE, [25..22], R
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field :ID9_DITHER_EN, [26], R
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field :ID9_DITHER_MODE, [28..27], R
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end
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*/
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static const struct dcn_dpp_shift tf_shift = {
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TF_REG_LIST_SH_MASK_DCN10(__SHIFT)
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TF_REG_LIST_SH_MASK_DCN10(__SHIFT),
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.CM_TEST_DEBUG_DATA_ID9_ICSC_MODE = 0x4
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};
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static const struct dcn_dpp_mask tf_mask = {
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TF_REG_LIST_SH_MASK_DCN10(_MASK),
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.CM_TEST_DEBUG_DATA_ID9_ICSC_MODE = 0x30
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};
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static const struct dcn_mpc_registers mpc_regs = {
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