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can: m_can: add missing delay after setting CCCR_INIT bit 

The spec mentions there may be a delay until the value written to INIT can be
read back due to the synchronization mechanism between the two clock domains.
But it does not indicate the exact clock cycles needed. The 5us delay is a
test value and seems ok.

Without the delay, CCCR.CCE bit may fail to be set and then the initialization
fail sometimes when do repeatly up and down.

Signed-off-by: Dong Aisheng <b29396@freescale.com>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
This commit is contained in:
Dong Aisheng 2014-10-29 18:45:24 +08:00 committed by Marc Kleine-Budde
parent 921f168109
commit 7660f63307
1 changed files with 1 additions and 0 deletions
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drivers/net/can/m_can/m_can.c
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@ -296,6 +296,7 @@ static inline void m_can_config_endisable(const struct m_can_priv *priv,
if (enable) {
/* enable m_can configuration */
m_can_write(priv, M_CAN_CCCR, cccr | CCCR_INIT);
udelay(5);
/* CCCR.CCE can only be set/reset while CCCR.INIT = '1' */
m_can_write(priv, M_CAN_CCCR, cccr | CCCR_INIT | CCCR_CCE);
} else {