p71924506
/
linux_old1
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

arm64: dts: exynos: configure GSCALER related clocks on TM2 

GSCALER should be feed with clock at certain rates.  Configure it on
Exynos5433 based TM2 board.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
This commit is contained in:
Andrzej Hajda 2019-03-20 14:07:01 +01:00 committed by Krzysztof Kozlowski
parent 9e98c678c2
commit 7698ffaf41
2 changed files with 10 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
View File

@ -289,6 +289,12 @@ &cmu_mfc {
assigned-clock-parents = <&cmu_top CLK_ACLK_MFC_400>; assigned-clock-parents = <&cmu_top CLK_ACLK_MFC_400>;
}; };
&cmu_mif {
assigned-clocks = <&cmu_mif CLK_MOUT_SCLK_DSD_A>, <&cmu_mif CLK_DIV_SCLK_DSD>;
assigned-clock-parents = <&cmu_mif CLK_MOUT_MFC_PLL_DIV2>;
assigned-clock-rates = <0>, <333000000>;
};
&cmu_mscl { &cmu_mscl {
assigned-clocks = <&cmu_mscl CLK_MOUT_ACLK_MSCL_400_USER>, assigned-clocks = <&cmu_mscl CLK_MOUT_ACLK_MSCL_400_USER>,
<&cmu_mscl CLK_MOUT_SCLK_JPEG_USER>, <&cmu_mscl CLK_MOUT_SCLK_JPEG_USER>,

6
arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
View File

@ -33,7 +33,8 @@ &cmu_disp {
<&cmu_disp CLK_MOUT_DISP_PLL>, <&cmu_disp CLK_MOUT_DISP_PLL>,
<&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>, <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>,
<&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>, <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>,
<&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>; <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>,
<&cmu_disp CLK_MOUT_SCLK_DSD_USER>;
assigned-clock-parents = <0>, <0>, assigned-clock-parents = <0>, <0>,
<&cmu_mif CLK_ACLK_DISP_333>, <&cmu_mif CLK_ACLK_DISP_333>,
<&cmu_mif CLK_SCLK_DSIM0_DISP>, <&cmu_mif CLK_SCLK_DSIM0_DISP>,
@ -45,7 +46,8 @@ &cmu_disp {
<&cmu_disp CLK_FOUT_DISP_PLL>, <&cmu_disp CLK_FOUT_DISP_PLL>,
<&cmu_mif CLK_MOUT_BUS_PLL_DIV2>, <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>,
<&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>, <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
<&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>; <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>,
<&cmu_mif CLK_SCLK_DSD_DISP>;
assigned-clock-rates = <250000000>, <400000000>; assigned-clock-rates = <250000000>, <400000000>;
}; };