dmaengine: imx-sdma: factor out a struct sdma_desc from struct sdma_channel
This is a preparation step to make the adding of virt-dma easier. We create a struct sdma_desc, move some fields from struct sdma_channel there and add a pointer from the former to the latter. For now we allocate the data statically in struct sdma_channel, but with virt-dma support it will be dynamically allocated. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Robin Gong <yibin.gong@nxp.com> Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de> Tested-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Sascha Hauer
Vinod Koul
parent
ce397d215c
commit
76c33d2707
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@ -288,6 +288,30 @@ struct sdma_context_data {
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struct sdma_engine;
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/**
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* struct sdma_desc - descriptor structor for one transfer
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* @vd descriptor for virt dma
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* @num_bd max NUM_BD. number of descriptors currently handling
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* @buf_tail ID of the buffer that was processed
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* @buf_ptail ID of the previous buffer that was processed
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* @period_len period length, used in cyclic.
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* @chn_real_count the real count updated from bd->mode.count
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* @chn_count the transfer count setuped
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* @sdmac sdma_channel pointer
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* @bd pointer of alloced bd
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*/
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struct sdma_desc {
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unsigned int num_bd;
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dma_addr_t bd_phys;
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unsigned int buf_tail;
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unsigned int buf_ptail;
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unsigned int period_len;
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unsigned int chn_real_count;
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unsigned int chn_count;
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struct sdma_channel *sdmac;
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struct sdma_buffer_descriptor *bd;
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};
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/**
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* struct sdma_channel - housekeeping for a SDMA channel
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*
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@ -298,11 +322,10 @@ struct sdma_engine;
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* @event_id0 aka dma request line
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* @event_id1 for channels that use 2 events
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* @word_size peripheral access size
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* @buf_tail ID of the buffer that was processed
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* @buf_ptail ID of the previous buffer that was processed
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* @num_bd max NUM_BD. number of descriptors currently handling
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*/
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struct sdma_channel {
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struct sdma_desc *desc;
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struct sdma_desc _desc;
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struct sdma_engine *sdma;
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unsigned int channel;
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enum dma_transfer_direction direction;
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@ -310,12 +333,6 @@ struct sdma_channel {
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unsigned int event_id0;
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unsigned int event_id1;
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enum dma_slave_buswidth word_size;
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unsigned int buf_tail;
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unsigned int buf_ptail;
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unsigned int num_bd;
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unsigned int period_len;
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struct sdma_buffer_descriptor *bd;
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dma_addr_t bd_phys;
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unsigned int pc_from_device, pc_to_device;
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unsigned int device_to_device;
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unsigned long flags;
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@ -325,10 +342,8 @@ struct sdma_channel {
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u32 shp_addr, per_addr;
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struct dma_chan chan;
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spinlock_t lock;
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struct dma_async_tx_descriptor desc;
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struct dma_async_tx_descriptor txdesc;
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enum dma_status status;
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unsigned int chn_count;
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unsigned int chn_real_count;
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struct tasklet_struct tasklet;
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struct imx_dma_data data;
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bool enabled;
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@ -391,6 +406,8 @@ struct sdma_engine {
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u32 spba_start_addr;
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u32 spba_end_addr;
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unsigned int irq;
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dma_addr_t bd0_phys;
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struct sdma_buffer_descriptor *bd0;
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};
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static struct sdma_driver_data sdma_imx31 = {
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@ -625,7 +642,7 @@ static int sdma_run_channel0(struct sdma_engine *sdma)
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static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size,
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u32 address)
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{
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struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
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struct sdma_buffer_descriptor *bd0 = sdma->bd0;
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void *buf_virt;
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dma_addr_t buf_phys;
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int ret;
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@ -700,7 +717,9 @@ static void sdma_update_channel_loop(struct sdma_channel *sdmac)
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* call callback function.
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*/
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while (1) {
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bd = &sdmac->bd[sdmac->buf_tail];
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struct sdma_desc *desc = sdmac->desc;
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bd = &desc->bd[desc->buf_tail];
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if (bd->mode.status & BD_DONE)
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break;
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@ -716,11 +735,11 @@ static void sdma_update_channel_loop(struct sdma_channel *sdmac)
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* the number of bytes present in the current buffer descriptor.
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*/
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sdmac->chn_real_count = bd->mode.count;
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desc->chn_real_count = bd->mode.count;
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bd->mode.status |= BD_DONE;
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bd->mode.count = sdmac->period_len;
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sdmac->buf_ptail = sdmac->buf_tail;
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sdmac->buf_tail = (sdmac->buf_tail + 1) % sdmac->num_bd;
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bd->mode.count = desc->period_len;
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desc->buf_ptail = desc->buf_tail;
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desc->buf_tail = (desc->buf_tail + 1) % desc->num_bd;
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/*
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* The callback is called from the interrupt context in order
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@ -729,7 +748,7 @@ static void sdma_update_channel_loop(struct sdma_channel *sdmac)
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* executed.
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*/
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dmaengine_desc_get_callback_invoke(&sdmac->desc, NULL);
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dmaengine_desc_get_callback_invoke(&sdmac->txdesc, NULL);
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if (error)
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sdmac->status = old_status;
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@ -742,17 +761,17 @@ static void mxc_sdma_handle_channel_normal(unsigned long data)
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struct sdma_buffer_descriptor *bd;
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int i, error = 0;
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sdmac->chn_real_count = 0;
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sdmac->desc->chn_real_count = 0;
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/*
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* non loop mode. Iterate over all descriptors, collect
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* errors and call callback function
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*/
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for (i = 0; i < sdmac->num_bd; i++) {
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bd = &sdmac->bd[i];
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for (i = 0; i < sdmac->desc->num_bd; i++) {
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bd = &sdmac->desc->bd[i];
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if (bd->mode.status & (BD_DONE | BD_RROR))
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error = -EIO;
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sdmac->chn_real_count += bd->mode.count;
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sdmac->desc->chn_real_count += bd->mode.count;
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}
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if (error)
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@ -760,9 +779,9 @@ static void mxc_sdma_handle_channel_normal(unsigned long data)
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else
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sdmac->status = DMA_COMPLETE;
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dma_cookie_complete(&sdmac->desc);
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dma_cookie_complete(&sdmac->txdesc);
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dmaengine_desc_get_callback_invoke(&sdmac->desc, NULL);
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dmaengine_desc_get_callback_invoke(&sdmac->txdesc, NULL);
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}
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static irqreturn_t sdma_int_handler(int irq, void *dev_id)
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@ -890,7 +909,7 @@ static int sdma_load_context(struct sdma_channel *sdmac)
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int channel = sdmac->channel;
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int load_address;
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struct sdma_context_data *context = sdma->context;
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struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
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struct sdma_buffer_descriptor *bd0 = sdma->bd0;
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int ret;
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unsigned long flags;
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@ -1093,18 +1112,22 @@ static int sdma_set_channel_priority(struct sdma_channel *sdmac,
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static int sdma_request_channel(struct sdma_channel *sdmac)
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{
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struct sdma_engine *sdma = sdmac->sdma;
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struct sdma_desc *desc;
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int channel = sdmac->channel;
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int ret = -EBUSY;
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sdmac->bd = dma_zalloc_coherent(NULL, PAGE_SIZE, &sdmac->bd_phys,
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sdmac->desc = &sdmac->_desc;
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desc = sdmac->desc;
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desc->bd = dma_zalloc_coherent(NULL, PAGE_SIZE, &desc->bd_phys,
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GFP_KERNEL);
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if (!sdmac->bd) {
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if (!desc->bd) {
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ret = -ENOMEM;
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goto out;
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}
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sdma->channel_control[channel].base_bd_ptr = sdmac->bd_phys;
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sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
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sdma->channel_control[channel].base_bd_ptr = desc->bd_phys;
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sdma->channel_control[channel].current_bd_ptr = desc->bd_phys;
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sdma_set_channel_priority(sdmac, MXC_SDMA_DEFAULT_PRIORITY);
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return 0;
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@ -1169,10 +1192,10 @@ static int sdma_alloc_chan_resources(struct dma_chan *chan)
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if (ret)
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goto disable_clk_ahb;
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dma_async_tx_descriptor_init(&sdmac->desc, chan);
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sdmac->desc.tx_submit = sdma_tx_submit;
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dma_async_tx_descriptor_init(&sdmac->txdesc, chan);
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sdmac->txdesc.tx_submit = sdma_tx_submit;
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/* txd.flags will be overwritten in prep funcs */
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sdmac->desc.flags = DMA_CTRL_ACK;
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sdmac->txdesc.flags = DMA_CTRL_ACK;
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return 0;
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@ -1187,6 +1210,7 @@ static void sdma_free_chan_resources(struct dma_chan *chan)
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{
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struct sdma_channel *sdmac = to_sdma_chan(chan);
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struct sdma_engine *sdma = sdmac->sdma;
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struct sdma_desc *desc = sdmac->desc;
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sdma_disable_channel(chan);
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@ -1200,7 +1224,7 @@ static void sdma_free_chan_resources(struct dma_chan *chan)
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sdma_set_channel_priority(sdmac, 0);
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dma_free_coherent(NULL, PAGE_SIZE, sdmac->bd, sdmac->bd_phys);
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dma_free_coherent(NULL, PAGE_SIZE, desc->bd, desc->bd_phys);
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clk_disable(sdma->clk_ipg);
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clk_disable(sdma->clk_ahb);
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@ -1216,6 +1240,7 @@ static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
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int ret, i, count;
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int channel = sdmac->channel;
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struct scatterlist *sg;
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struct sdma_desc *desc = sdmac->desc;
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if (sdmac->status == DMA_IN_PROGRESS)
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return NULL;
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@ -1223,9 +1248,9 @@ static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
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sdmac->flags = 0;
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sdmac->buf_tail = 0;
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sdmac->buf_ptail = 0;
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sdmac->chn_real_count = 0;
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desc->buf_tail = 0;
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desc->buf_ptail = 0;
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desc->chn_real_count = 0;
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dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n",
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sg_len, channel);
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@ -1242,9 +1267,9 @@ static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
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goto err_out;
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}
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sdmac->chn_count = 0;
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desc->chn_count = 0;
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for_each_sg(sgl, sg, sg_len, i) {
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struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
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struct sdma_buffer_descriptor *bd = &desc->bd[i];
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int param;
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bd->buffer_addr = sg->dma_address;
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@ -1259,7 +1284,7 @@ static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
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}
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bd->mode.count = count;
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sdmac->chn_count += count;
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desc->chn_count += count;
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if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) {
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ret = -EINVAL;
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@ -1300,10 +1325,10 @@ static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
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bd->mode.status = param;
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}
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sdmac->num_bd = sg_len;
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sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
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desc->num_bd = sg_len;
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sdma->channel_control[channel].current_bd_ptr = desc->bd_phys;
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return &sdmac->desc;
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return &sdmac->txdesc;
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err_out:
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sdmac->status = DMA_ERROR;
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return NULL;
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@ -1319,6 +1344,7 @@ static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic(
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int num_periods = buf_len / period_len;
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int channel = sdmac->channel;
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int ret, i = 0, buf = 0;
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struct sdma_desc *desc = sdmac->desc;
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dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel);
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@ -1327,10 +1353,10 @@ static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic(
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sdmac->status = DMA_IN_PROGRESS;
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sdmac->buf_tail = 0;
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sdmac->buf_ptail = 0;
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sdmac->chn_real_count = 0;
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sdmac->period_len = period_len;
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desc->buf_tail = 0;
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desc->buf_ptail = 0;
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desc->chn_real_count = 0;
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desc->period_len = period_len;
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sdmac->flags |= IMX_DMA_SG_LOOP;
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sdmac->direction = direction;
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@ -1351,7 +1377,7 @@ static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic(
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}
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while (buf < buf_len) {
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struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
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struct sdma_buffer_descriptor *bd = &desc->bd[i];
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int param;
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bd->buffer_addr = dma_addr;
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@ -1382,10 +1408,10 @@ static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic(
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i++;
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}
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sdmac->num_bd = num_periods;
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sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
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desc->num_bd = num_periods;
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sdma->channel_control[channel].current_bd_ptr = desc->bd_phys;
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return &sdmac->desc;
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return &sdmac->txdesc;
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err_out:
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sdmac->status = DMA_ERROR;
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return NULL;
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@ -1424,13 +1450,14 @@ static enum dma_status sdma_tx_status(struct dma_chan *chan,
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struct dma_tx_state *txstate)
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{
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struct sdma_channel *sdmac = to_sdma_chan(chan);
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struct sdma_desc *desc = sdmac->desc;
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u32 residue;
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if (sdmac->flags & IMX_DMA_SG_LOOP)
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residue = (sdmac->num_bd - sdmac->buf_ptail) *
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sdmac->period_len - sdmac->chn_real_count;
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residue = (desc->num_bd - desc->buf_ptail) *
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desc->period_len - desc->chn_real_count;
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else
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residue = sdmac->chn_count - sdmac->chn_real_count;
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residue = desc->chn_count - desc->chn_real_count;
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dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie,
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residue);
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@ -1654,6 +1681,8 @@ static int sdma_init(struct sdma_engine *sdma)
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if (ret)
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goto err_dma_alloc;
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sdma->bd0 = sdma->channel[0].desc->bd;
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sdma_config_ownership(&sdma->channel[0], false, true, false);
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/* Set Command Channel (Channel Zero) */
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