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Merge branch 'mailbox-for-next' of git://git.linaro.org/landing-teams/working/fujitsu/integration 

Pull mailbox updates from Jussi Brar:
 "Broadcom:
   - New PDC controller driver and bindings

  Misc:
   - PL320 - Convert from 'raw' IO to 'relaxed' version
   - Test - fix dangling pointer"

* 'mailbox-for-next' of git://git.linaro.org/landing-teams/working/fujitsu/integration:
  mailbox: Fix format and type mismatches in Broadcom PDC driver
  mailbox: Add Broadcom PDC mailbox driver
  dt-bindings: add bindings documentation for PDC driver.
  mailbox: pl320: remove __raw IO
  mailbox: mailbox-test: set tdev->signal to NULL after freeing
This commit is contained in:
Linus Torvalds 2016-08-01 07:23:29 -04:00
parent 07f00f06ba a68b216676
commit 77d9ada23f
7 changed files with 1645 additions and 23 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

23
Documentation/devicetree/bindings/mailbox/brcm,iproc-pdc-mbox.txt Normal file
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@ -0,0 +1,23 @@
The PDC driver manages data transfer to and from various offload engines
on some Broadcom SoCs. An SoC may have multiple PDC hardware blocks. There is
one device tree entry per block.
Required properties:
- compatible : Should be "brcm,iproc-pdc-mbox".
- reg: Should contain PDC registers location and length.
- interrupts: Should contain the IRQ line for the PDC.
- #mbox-cells: 1
- brcm,rx-status-len: Length of metadata preceding received frames, in bytes.
Optional properties:
- brcm,use-bcm-hdr: present if a BCM header precedes each frame.
Example:
pdc0: iproc-pdc0@0x612c0000 {
compatible = "brcm,iproc-pdc-mbox";
reg = <0 0x612c0000 0 0x445>; /* PDC FS0 regs */
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <1>; /* one cell per mailbox channel */
brcm,rx-status-len = <32>;
brcm,use-bcm-hdr;
};

9
drivers/mailbox/Kconfig
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@ -123,4 +123,13 @@ config XGENE_SLIMPRO_MBOX
It is used to send short messages between ARM64-bit cores and
the SLIMpro Management Engine, primarily for PM. Say Y here if you
want to use the APM X-Gene SLIMpro IPCM support.
config BCM_PDC_MBOX
tristate "Broadcom PDC Mailbox"
depends on ARM64 || COMPILE_TEST
default ARCH_BCM_IPROC
help
Mailbox implementation for the Broadcom PDC ring manager,
which provides access to various offload engines on Broadcom
SoCs. Say Y here if you want to use the Broadcom PDC.
endif

2
drivers/mailbox/Makefile
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@ -25,3 +25,5 @@ obj-$(CONFIG_TI_MESSAGE_MANAGER) += ti-msgmgr.o
obj-$(CONFIG_XGENE_SLIMPRO_MBOX) += mailbox-xgene-slimpro.o
obj-$(CONFIG_HI6220_MBOX) += hi6220-mailbox.o
obj-$(CONFIG_BCM_PDC_MBOX) += bcm-pdc-mailbox.o

1531
drivers/mailbox/bcm-pdc-mailbox.c Normal file
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File diff suppressed because it is too large Load Diff

1
drivers/mailbox/mailbox-test.c
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@ -133,6 +133,7 @@ static ssize_t mbox_test_message_write(struct file *filp,
out:
kfree(tdev->signal);
kfree(tdev->message);
tdev->signal = NULL;
return ret < 0 ? ret : count;
}

46
drivers/mailbox/pl320-ipc.c
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@ -58,29 +58,29 @@ static ATOMIC_NOTIFIER_HEAD(ipc_notifier);
static inline void set_destination(int source, int mbox)
{
__raw_writel(CHAN_MASK(source), ipc_base + IPCMxDSET(mbox));
__raw_writel(CHAN_MASK(source), ipc_base + IPCMxMSET(mbox));
writel_relaxed(CHAN_MASK(source), ipc_base + IPCMxDSET(mbox));
writel_relaxed(CHAN_MASK(source), ipc_base + IPCMxMSET(mbox));
}
static inline void clear_destination(int source, int mbox)
{
__raw_writel(CHAN_MASK(source), ipc_base + IPCMxDCLEAR(mbox));
__raw_writel(CHAN_MASK(source), ipc_base + IPCMxMCLEAR(mbox));
writel_relaxed(CHAN_MASK(source), ipc_base + IPCMxDCLEAR(mbox));
writel_relaxed(CHAN_MASK(source), ipc_base + IPCMxMCLEAR(mbox));
}
static void __ipc_send(int mbox, u32 *data)
{
int i;
for (i = 0; i < 7; i++)
__raw_writel(data[i], ipc_base + IPCMxDR(mbox, i));
__raw_writel(0x1, ipc_base + IPCMxSEND(mbox));
writel_relaxed(data[i], ipc_base + IPCMxDR(mbox, i));
writel_relaxed(0x1, ipc_base + IPCMxSEND(mbox));
}
static u32 __ipc_rcv(int mbox, u32 *data)
{
int i;
for (i = 0; i < 7; i++)
data[i] = __raw_readl(ipc_base + IPCMxDR(mbox, i));
data[i] = readl_relaxed(ipc_base + IPCMxDR(mbox, i));
return data[1];
}
@ -112,15 +112,15 @@ static irqreturn_t ipc_handler(int irq, void *dev)
u32 irq_stat;
u32 data[7];
irq_stat = __raw_readl(ipc_base + IPCMMIS(1));
irq_stat = readl_relaxed(ipc_base + IPCMMIS(1));
if (irq_stat & MBOX_MASK(IPC_TX_MBOX)) {
__raw_writel(0, ipc_base + IPCMxSEND(IPC_TX_MBOX));
writel_relaxed(0, ipc_base + IPCMxSEND(IPC_TX_MBOX));
complete(&ipc_completion);
}
if (irq_stat & MBOX_MASK(IPC_RX_MBOX)) {
__ipc_rcv(IPC_RX_MBOX, data);
atomic_notifier_call_chain(&ipc_notifier, data[0], data + 1);
__raw_writel(2, ipc_base + IPCMxSEND(IPC_RX_MBOX));
writel_relaxed(2, ipc_base + IPCMxSEND(IPC_RX_MBOX));
}
return IRQ_HANDLED;
@ -146,7 +146,7 @@ static int pl320_probe(struct amba_device *adev, const struct amba_id *id)
if (ipc_base == NULL)
return -ENOMEM;
__raw_writel(0, ipc_base + IPCMxSEND(IPC_TX_MBOX));
writel_relaxed(0, ipc_base + IPCMxSEND(IPC_TX_MBOX));
ipc_irq = adev->irq[0];
ret = request_irq(ipc_irq, ipc_handler, 0, dev_name(&adev->dev), NULL);
@ -154,20 +154,20 @@ static int pl320_probe(struct amba_device *adev, const struct amba_id *id)
goto err;
/* Init slow mailbox */
__raw_writel(CHAN_MASK(A9_SOURCE),
ipc_base + IPCMxSOURCE(IPC_TX_MBOX));
__raw_writel(CHAN_MASK(M3_SOURCE),
ipc_base + IPCMxDSET(IPC_TX_MBOX));
__raw_writel(CHAN_MASK(M3_SOURCE) | CHAN_MASK(A9_SOURCE),
ipc_base + IPCMxMSET(IPC_TX_MBOX));
writel_relaxed(CHAN_MASK(A9_SOURCE),
ipc_base + IPCMxSOURCE(IPC_TX_MBOX));
writel_relaxed(CHAN_MASK(M3_SOURCE),
ipc_base + IPCMxDSET(IPC_TX_MBOX));
writel_relaxed(CHAN_MASK(M3_SOURCE) | CHAN_MASK(A9_SOURCE),
ipc_base + IPCMxMSET(IPC_TX_MBOX));
/* Init receive mailbox */
__raw_writel(CHAN_MASK(M3_SOURCE),
ipc_base + IPCMxSOURCE(IPC_RX_MBOX));
__raw_writel(CHAN_MASK(A9_SOURCE),
ipc_base + IPCMxDSET(IPC_RX_MBOX));
__raw_writel(CHAN_MASK(M3_SOURCE) | CHAN_MASK(A9_SOURCE),
ipc_base + IPCMxMSET(IPC_RX_MBOX));
writel_relaxed(CHAN_MASK(M3_SOURCE),
ipc_base + IPCMxSOURCE(IPC_RX_MBOX));
writel_relaxed(CHAN_MASK(A9_SOURCE),
ipc_base + IPCMxDSET(IPC_RX_MBOX));
writel_relaxed(CHAN_MASK(M3_SOURCE) | CHAN_MASK(A9_SOURCE),
ipc_base + IPCMxMSET(IPC_RX_MBOX));
return 0;
err:

56
include/linux/mailbox/brcm-message.h Normal file
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@ -0,0 +1,56 @@
/*
* Copyright (C) 2016 Broadcom
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Common header for Broadcom mailbox messages which is shared across
* Broadcom SoCs and Broadcom mailbox client drivers.
*/
#ifndef _LINUX_BRCM_MESSAGE_H_
#define _LINUX_BRCM_MESSAGE_H_
#include <linux/scatterlist.h>
enum brcm_message_type {
BRCM_MESSAGE_UNKNOWN = 0,
BRCM_MESSAGE_SPU,
BRCM_MESSAGE_SBA,
BRCM_MESSAGE_MAX,
};
struct brcm_sba_command {
u64 cmd;
#define BRCM_SBA_CMD_TYPE_A BIT(0)
#define BRCM_SBA_CMD_TYPE_B BIT(1)
#define BRCM_SBA_CMD_TYPE_C BIT(2)
#define BRCM_SBA_CMD_HAS_RESP BIT(3)
#define BRCM_SBA_CMD_HAS_OUTPUT BIT(4)
u64 flags;
dma_addr_t input;
size_t input_len;
dma_addr_t resp;
size_t resp_len;
dma_addr_t output;
size_t output_len;
};
struct brcm_message {
enum brcm_message_type type;
union {
struct {
struct scatterlist *src;
struct scatterlist *dst;
} spu;
struct {
struct brcm_sba_command *cmds;
unsigned int cmds_count;
} sba;
};
void *ctx;
int error;
};
#endif /* _LINUX_BRCM_MESSAGE_H_ */