This pull request contains Device Tree changes for Broadcom ARM64-based SoCS:
- Anup adds nodes for the AHCI and SATA3 PHY peripherals to the Northstar2 SoCs - Dhanajay enables pinctrl for the Northstar2 SoCs - Jon Mason enables all of the UART peripherals found in the NS2 SVK and finally adds the CCI-400 and PMU nodes -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJXY1QtAAoJEIfQlpxEBwcEOk4QAObsEiL/mCR0mx/6+QC0kivU LRrfHKKkMOjpvGZaY9I19CW3toWZB5Nr7B8FtsEQf/Nwp35ug4e0ajPw52DGuvyU 1xhWHwQ7rIPP9FU3/1wHZ1Na26m9GeN1RAr7ljHCymOaK0yyFNWvP6GQs1ZyYZsf kc4NjRU4gckNi5ouYtdPM5DtU1OGeXk4jesX8PEZJ/C4DxhIpIod6pgZRmxxw6p8 6MLra/ZccNHsSUoc0OV66GYLc02TRNGejB9vIVNl6QyoNabsEWRXMNEdM0Zn9i80 nF8kZvwYS1333wS1p5RilwFMOfE2qF0MzYFnwDgOqdk0D7ugoEE/Y1lYolce2u1p rTdf3y4QpRnRWAf+SwcGcJZE4XZ6kY19qBfvGv3kbRKnPTVMVME+w7vYQdGyPcMz jxgU1gaAqK/nHoCnOuh0GoP5PROlJOLXyC2ivRUehsnfg+0U6XU+jjtj9H5cnq20 ZQSv8uwqeppu7uPyh3BChrc1Zm78fUQRYcqOvtJkrttub+oeVN/tWIIkUu9t1m89 vBJe3zixuN/EghMn85sLimB+yEu7ETTujgvGtbp6Wp7ku5+7RbDJy+QlbdDZho8K JYfLq2kCW6KBrrIXyrvYrbTv/vys5bFaZ88XcHYNs657xVR+rxUov8O9jvNEqbxp qSrWCfaMyLqOV1VCrf5s =296G -----END PGP SIGNATURE----- Merge tag 'arm-soc/for-4.8/devicetree-arm64' of http://github.com/Broadcom/stblinux into next/dt64 This pull request contains Device Tree changes for Broadcom ARM64-based SoCS: - Anup adds nodes for the AHCI and SATA3 PHY peripherals to the Northstar2 SoCs - Dhanajay enables pinctrl for the Northstar2 SoCs - Jon Mason enables all of the UART peripherals found in the NS2 SVK and finally adds the CCI-400 and PMU nodes * tag 'arm-soc/for-4.8/devicetree-arm64' of http://github.com/Broadcom/stblinux: arm64: dts: NS2: Add CCI-400 PMU support arm64: dts: NS2: Add all of the UARTs arm64: dts: Enable GPIO for Broadcom NS2 SoC arm64: dts: enable pinctrl for Broadcom NS2 SoC arm64: dts: Add SATA3 AHCI and SATA3 PHY DT nodes for NS2 dt-bindings: ata: add compatible string for iProc AHCI controller Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
7a4fad480d
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@ -10,6 +10,7 @@ PHYs.
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Required properties:
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- compatible : compatible string, one of:
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- "allwinner,sun4i-a10-ahci"
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- "brcm,iproc-ahci"
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- "hisilicon,hisi-ahci"
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- "cavium,octeon-7130-ahci"
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- "ibm,476gtr-ahci"
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@ -40,10 +40,14 @@ / {
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aliases {
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serial0 = &uart3;
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serial1 = &uart0;
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serial2 = &uart1;
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serial3 = &uart2;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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bootargs = "earlycon=uart8250,mmio32,0x66130000";
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};
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memory {
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@ -68,6 +72,18 @@ &i2c1 {
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status = "ok";
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};
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&uart0 {
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status = "ok";
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};
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&uart1 {
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status = "ok";
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};
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&uart2 {
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status = "ok";
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};
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&uart3 {
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status = "ok";
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};
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@ -117,6 +133,18 @@ at25@0 {
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};
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};
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&sata_phy0 {
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status = "ok";
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};
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&sata_phy1 {
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status = "ok";
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};
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&sata {
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status = "ok";
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};
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&sdio0 {
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status = "ok";
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};
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@ -132,3 +160,12 @@ nandcs@0 {
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#size-cells = <1>;
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};
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};
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&pinctrl {
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pinctrl-names = "default";
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pinctrl-0 = <&nand_sel>;
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nand_sel: nand_sel {
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function = "nand";
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groups = "nand_grp";
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};
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};
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@ -251,6 +251,22 @@ smmu: mmu@64000000 {
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mmu-masters;
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};
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pinctrl: pinctrl@6501d130 {
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compatible = "brcm,ns2-pinmux";
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reg = <0x6501d130 0x08>,
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<0x660a0028 0x04>,
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<0x660009b0 0x40>;
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};
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gpio_aon: gpio@65024800 {
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compatible = "brcm,iproc-gpio";
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reg = <0x65024800 0x50>,
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<0x65024008 0x18>;
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ngpios = <6>;
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#gpio-cells = <2>;
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gpio-controller;
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};
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gic: interrupt-controller@65210000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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@ -263,6 +279,26 @@ gic: interrupt-controller@65210000 {
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IRQ_TYPE_LEVEL_HIGH)>;
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};
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cci@65590000 {
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compatible = "arm,cci-400";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x65590000 0x1000>;
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ranges = <0 0x65590000 0x10000>;
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pmu@9000 {
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compatible = "arm,cci-400-pmu,r1",
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"arm,cci-400-pmu";
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reg = <0x9000 0x4000>;
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interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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timer0: timer@66030000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0x66030000 0x1000>;
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@ -321,6 +357,16 @@ wdt0: watchdog@66090000 {
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clock-names = "wdogclk", "apb_pclk";
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};
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gpio_g: gpio@660a0000 {
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compatible = "brcm,iproc-gpio";
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reg = <0x660a0000 0x50>;
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ngpios = <32>;
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#gpio-cells = <2>;
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gpio-controller;
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interrupt-controller;
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interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>;
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};
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i2c1: i2c@660b0000 {
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compatible = "brcm,iproc-i2c";
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reg = <0x660b0000 0x100>;
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@ -331,6 +377,36 @@ i2c1: i2c@660b0000 {
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status = "disabled";
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};
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uart0: serial@66100000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x66100000 0x100>;
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interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&iprocslow>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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uart1: serial@66110000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x66110000 0x100>;
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interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&iprocslow>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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uart2: serial@66120000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x66120000 0x100>;
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interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&iprocslow>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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uart3: serial@66130000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x66130000 0x100>;
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@ -368,6 +444,49 @@ hwrng: hwrng@66220000 {
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reg = <0x66220000 0x28>;
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};
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sata_phy: sata_phy@663f0100 {
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compatible = "brcm,iproc-ns2-sata-phy";
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reg = <0x663f0100 0x1f00>,
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<0x663f004c 0x10>;
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reg-names = "phy", "phy-ctrl";
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#address-cells = <1>;
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#size-cells = <0>;
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sata_phy0: sata-phy@0 {
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reg = <0>;
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#phy-cells = <0>;
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status = "disabled";
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};
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sata_phy1: sata-phy@1 {
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reg = <1>;
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#phy-cells = <0>;
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status = "disabled";
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};
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};
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sata: ahci@663f2000 {
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compatible = "brcm,iproc-ahci", "generic-ahci";
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reg = <0x663f2000 0x1000>;
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reg-names = "ahci";
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interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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sata0: sata-port@0 {
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reg = <0>;
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phys = <&sata_phy0>;
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phy-names = "sata-phy";
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};
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sata1: sata-port@1 {
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reg = <1>;
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phys = <&sata_phy1>;
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phy-names = "sata-phy";
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};
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};
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sdio0: sdhci@66420000 {
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compatible = "brcm,sdhci-iproc-cygnus";
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reg = <0x66420000 0x100>;
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