drm/amd/amdgpu: Add some documentation to the debugfs entries
Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Tom St Denis
Alex Deucher
parent
dfe8a0187c
commit
7e4237dbe4
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@ -28,8 +28,13 @@
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#include <linux/debugfs.h>
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#include "amdgpu.h"
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/*
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* Debugfs
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/**
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* amdgpu_debugfs_add_files - Add simple debugfs entries
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*
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* @adev: Device to attach debugfs entries to
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* @files: Array of function callbacks that respond to reads
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* @nfiles: Number of callbacks to register
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*
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*/
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int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
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const struct drm_info_list *files,
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@ -64,7 +69,33 @@ int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
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#if defined(CONFIG_DEBUG_FS)
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/**
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* amdgpu_debugfs_process_reg_op - Handle MMIO register reads/writes
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*
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* @read: True if reading
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* @f: open file handle
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* @buf: User buffer to write/read to
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* @size: Number of bytes to write/read
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* @pos: Offset to seek to
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*
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* This debugfs entry has special meaning on the offset being sought.
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* Various bits have different meanings:
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*
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* Bit 62: Indicates a GRBM bank switch is needed
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* Bit 61: Indicates a SRBM bank switch is needed (implies bit 62 is
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* zero)
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* Bits 24..33: The SE or ME selector if needed
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* Bits 34..43: The SH (or SA) or PIPE selector if needed
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* Bits 44..53: The INSTANCE (or CU/WGP) or QUEUE selector if needed
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*
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* Bit 23: Indicates that the PM power gating lock should be held
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* This is necessary to read registers that might be
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* unreliable during a power gating transistion.
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*
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* The lower bits are the BYTE offset of the register to read. This
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* allows reading multiple registers in a single call and having
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* the returned size reflect that.
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*/
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static int amdgpu_debugfs_process_reg_op(bool read, struct file *f,
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char __user *buf, size_t size, loff_t *pos)
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{
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@ -164,19 +195,37 @@ static int amdgpu_debugfs_process_reg_op(bool read, struct file *f,
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return result;
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}
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/**
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* amdgpu_debugfs_regs_read - Callback for reading MMIO registers
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*/
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static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
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size_t size, loff_t *pos)
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{
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return amdgpu_debugfs_process_reg_op(true, f, buf, size, pos);
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}
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/**
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* amdgpu_debugfs_regs_write - Callback for writing MMIO registers
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*/
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static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf,
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size_t size, loff_t *pos)
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{
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return amdgpu_debugfs_process_reg_op(false, f, (char __user *)buf, size, pos);
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}
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/**
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* amdgpu_debugfs_regs_pcie_read - Read from a PCIE register
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*
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* @f: open file handle
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* @buf: User buffer to store read data in
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* @size: Number of bytes to read
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* @pos: Offset to seek to
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*
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* The lower bits are the BYTE offset of the register to read. This
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* allows reading multiple registers in a single call and having
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* the returned size reflect that.
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*/
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static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf,
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size_t size, loff_t *pos)
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{
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@ -204,6 +253,18 @@ static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf,
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return result;
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}
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/**
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* amdgpu_debugfs_regs_pcie_write - Write to a PCIE register
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*
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* @f: open file handle
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* @buf: User buffer to write data from
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* @size: Number of bytes to write
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* @pos: Offset to seek to
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*
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* The lower bits are the BYTE offset of the register to write. This
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* allows writing multiple registers in a single call and having
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* the returned size reflect that.
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*/
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static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user *buf,
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size_t size, loff_t *pos)
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{
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@ -232,6 +293,18 @@ static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user
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return result;
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}
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/**
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* amdgpu_debugfs_regs_didt_read - Read from a DIDT register
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*
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* @f: open file handle
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* @buf: User buffer to store read data in
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* @size: Number of bytes to read
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* @pos: Offset to seek to
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*
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* The lower bits are the BYTE offset of the register to read. This
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* allows reading multiple registers in a single call and having
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* the returned size reflect that.
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*/
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static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf,
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size_t size, loff_t *pos)
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{
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@ -259,6 +332,18 @@ static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf,
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return result;
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}
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/**
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* amdgpu_debugfs_regs_didt_write - Write to a DIDT register
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*
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* @f: open file handle
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* @buf: User buffer to write data from
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* @size: Number of bytes to write
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* @pos: Offset to seek to
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*
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* The lower bits are the BYTE offset of the register to write. This
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* allows writing multiple registers in a single call and having
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* the returned size reflect that.
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*/
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static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user *buf,
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size_t size, loff_t *pos)
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{
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@ -287,6 +372,18 @@ static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user
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return result;
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}
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/**
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* amdgpu_debugfs_regs_smc_read - Read from a SMC register
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*
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* @f: open file handle
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* @buf: User buffer to store read data in
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* @size: Number of bytes to read
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* @pos: Offset to seek to
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*
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* The lower bits are the BYTE offset of the register to read. This
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* allows reading multiple registers in a single call and having
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* the returned size reflect that.
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*/
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static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf,
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size_t size, loff_t *pos)
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{
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@ -314,6 +411,18 @@ static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf,
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return result;
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}
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/**
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* amdgpu_debugfs_regs_smc_write - Write to a SMC register
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*
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* @f: open file handle
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* @buf: User buffer to write data from
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* @size: Number of bytes to write
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* @pos: Offset to seek to
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*
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* The lower bits are the BYTE offset of the register to write. This
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* allows writing multiple registers in a single call and having
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* the returned size reflect that.
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*/
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static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user *buf,
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size_t size, loff_t *pos)
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{
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@ -342,6 +451,20 @@ static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user *
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return result;
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}
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/**
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* amdgpu_debugfs_gca_config_read - Read from gfx config data
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*
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* @f: open file handle
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* @buf: User buffer to store read data in
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* @size: Number of bytes to read
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* @pos: Offset to seek to
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*
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* This file is used to access configuration data in a somewhat
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* stable fashion. The format is a series of DWORDs with the first
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* indicating which revision it is. New content is appended to the
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* end so that older software can still read the data.
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*/
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static ssize_t amdgpu_debugfs_gca_config_read(struct file *f, char __user *buf,
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size_t size, loff_t *pos)
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{
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@ -418,6 +541,19 @@ static ssize_t amdgpu_debugfs_gca_config_read(struct file *f, char __user *buf,
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return result;
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}
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/**
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* amdgpu_debugfs_sensor_read - Read from the powerplay sensors
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*
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* @f: open file handle
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* @buf: User buffer to store read data in
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* @size: Number of bytes to read
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* @pos: Offset to seek to
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*
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* The offset is treated as the BYTE address of one of the sensors
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* enumerated in amd/include/kgd_pp_interface.h under the
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* 'amd_pp_sensors' enumeration. For instance to read the UVD VCLK
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* you would use the offset 3 * 4 = 12.
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*/
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static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf,
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size_t size, loff_t *pos)
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{
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@ -457,6 +593,27 @@ static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf,
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return !r ? outsize : r;
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}
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/** amdgpu_debugfs_wave_read - Read WAVE STATUS data
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*
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* @f: open file handle
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* @buf: User buffer to store read data in
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* @size: Number of bytes to read
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* @pos: Offset to seek to
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*
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* The offset being sought changes which wave that the status data
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* will be returned for. The bits are used as follows:
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*
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* Bits 0..6: Byte offset into data
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* Bits 7..14: SE selector
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* Bits 15..22: SH/SA selector
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* Bits 23..30: CU/{WGP+SIMD} selector
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* Bits 31..36: WAVE ID selector
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* Bits 37..44: SIMD ID selector
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*
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* The returned data begins with one DWORD of version information
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* Followed by WAVE STATUS registers relevant to the GFX IP version
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* being used. See gfx_v8_0_read_wave_data() for an example output.
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*/
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static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf,
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size_t size, loff_t *pos)
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{
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@ -507,6 +664,28 @@ static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf,
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return result;
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}
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/** amdgpu_debugfs_gpr_read - Read wave gprs
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*
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* @f: open file handle
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* @buf: User buffer to store read data in
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* @size: Number of bytes to read
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* @pos: Offset to seek to
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*
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* The offset being sought changes which wave that the status data
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* will be returned for. The bits are used as follows:
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*
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* Bits 0..11: Byte offset into data
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* Bits 12..19: SE selector
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* Bits 20..27: SH/SA selector
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* Bits 28..35: CU/{WGP+SIMD} selector
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* Bits 36..43: WAVE ID selector
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* Bits 37..44: SIMD ID selector
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* Bits 52..59: Thread selector
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* Bits 60..61: Bank selector (VGPR=0,SGPR=1)
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*
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* The return data comes from the SGPR or VGPR register bank for
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* the selected operational unit.
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*/
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static ssize_t amdgpu_debugfs_gpr_read(struct file *f, char __user *buf,
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size_t size, loff_t *pos)
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{
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@ -637,6 +816,12 @@ static const char *debugfs_regs_names[] = {
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"amdgpu_gpr",
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};
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/**
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* amdgpu_debugfs_regs_init - Initialize debugfs entries that provide
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* register access.
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*
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* @adev: The device to attach the debugfs entries to
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*/
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int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
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{
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struct drm_minor *minor = adev->ddev->primary;
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