clk: tegra: Changes for v5.1-rc1
This contains a couple of prerequisite patches to enable CPU frequency scaling on Tegra210. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAlxdl3ETHHRyZWRpbmdA bnZpZGlhLmNvbQAKCRDdI6zXfz6zoSjGD/sFNbFXRycqN+PlwvvMK6b+rRRpHEVb Wv8cpO/JgKGCEcXIbmY25xgouJzVgAH0SxmJ0P2l5PO28saUAMv2+7jzRiXTqTxH uAF7MFVUYRcXzULckZTzIQz8mzek8B2Ma/8gRVxM2LFkfCPpXGxweuNU6z+pFz9o L31SIA64dqLuDnWN10aK28fwb6zkXN1ULwrRBXBeU9kaA7W6xAm7RLOmxnA6uaxQ kHtNaF49vq8l3EX3rPMmEAgYdMOWylk4JPyFhGq10M9viUcxQV2PXBlBBQTU9gLH DpnNhwb3yAC/cmjs1yakTJySo0KyyvxnS6DdiRPkLYPkxZJCZRCZqG+E0AW7r5+I uoybiRv0RgUtz2naM1JR/US8dGakRXM71LGNQ3OCTfGI/YynsbTX0qyC3d/owAbg LKgOpDqpR3a6SpS8OM8wskAgHtW7DzbncnPV9Axp3pAd04MaI2jClW9DUO0EL5QT 1v6eEQRa5rdpgY1sxDYRNNsKxtpA8dC3i8mujWA85p1z9CCFnJxkHhr169xOSwRS vlZjeMM23gSQIDvW86tIwB27oraYyzQGuJfHw8V2Z5tw+FJ2ajBdgVZUEH/F5/xk BVHMyC+MHGwaQGUSTq1SsHRPK9/OREmH/zxfIj/s/wR72UcImJ4ih56yOZFCNFUz pAHHj9XjGmfzKQ== =R+Ez -----END PGP SIGNATURE----- Merge tag 'tegra-for-5.1-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers clk: tegra: Changes for v5.1-rc1 This contains a couple of prerequisite patches to enable CPU frequency scaling on Tegra210. * tag 'tegra-for-5.1-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: clk: tegra: dfll: build clk-dfll.c for Tegra124 and Tegra210 clk: tegra: dfll: add CVB tables for Tegra210 clk: tegra: dfll: round down voltages based on alignment clk: tegra: dfll: support PWM regulator control clk: tegra: dfll: CVB calculation alignment with the regulator clk: tegra: dfll: registration for multiple SoCs Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
7e5c4c26c7
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@ -5,3 +5,8 @@ config TEGRA_CLK_EMC
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config CLK_TEGRA_BPMP
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def_bool y
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depends on TEGRA_BPMP
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config TEGRA_CLK_DFLL
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depends on ARCH_TEGRA_124_SOC || ARCH_TEGRA_210_SOC
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select PM_OPP
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def_bool y
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@ -20,7 +20,7 @@ obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += clk-tegra20.o
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obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += clk-tegra30.o
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obj-$(CONFIG_ARCH_TEGRA_114_SOC) += clk-tegra114.o
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obj-$(CONFIG_ARCH_TEGRA_124_SOC) += clk-tegra124.o
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obj-$(CONFIG_ARCH_TEGRA_124_SOC) += clk-tegra124-dfll-fcpu.o
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obj-$(CONFIG_TEGRA_CLK_DFLL) += clk-tegra124-dfll-fcpu.o
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obj-$(CONFIG_ARCH_TEGRA_132_SOC) += clk-tegra124.o
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obj-y += cvb.o
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obj-$(CONFIG_ARCH_TEGRA_210_SOC) += clk-tegra210.o
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@ -1,7 +1,7 @@
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/*
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* clk-dfll.c - Tegra DFLL clock source common code
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*
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* Copyright (C) 2012-2014 NVIDIA Corporation. All rights reserved.
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* Copyright (C) 2012-2019 NVIDIA Corporation. All rights reserved.
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*
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* Aleksandr Frid <afrid@nvidia.com>
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* Paul Walmsley <pwalmsley@nvidia.com>
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@ -47,6 +47,7 @@
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/pm_opp.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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@ -243,6 +244,12 @@ enum dfll_tune_range {
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DFLL_TUNE_LOW = 1,
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};
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enum tegra_dfll_pmu_if {
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TEGRA_DFLL_PMU_I2C = 0,
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TEGRA_DFLL_PMU_PWM = 1,
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};
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/**
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* struct dfll_rate_req - target DFLL rate request data
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* @rate: target frequency, after the postscaling
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@ -300,10 +307,19 @@ struct tegra_dfll {
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u32 i2c_reg;
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u32 i2c_slave_addr;
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/* i2c_lut array entries are regulator framework selectors */
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unsigned i2c_lut[MAX_DFLL_VOLTAGES];
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int i2c_lut_size;
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u8 lut_min, lut_max, lut_safe;
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/* lut array entries are regulator framework selectors or PWM values*/
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unsigned lut[MAX_DFLL_VOLTAGES];
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unsigned long lut_uv[MAX_DFLL_VOLTAGES];
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int lut_size;
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u8 lut_bottom, lut_min, lut_max, lut_safe;
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/* PWM interface */
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enum tegra_dfll_pmu_if pmu_if;
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unsigned long pwm_rate;
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struct pinctrl *pwm_pin;
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struct pinctrl_state *pwm_enable_state;
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struct pinctrl_state *pwm_disable_state;
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u32 reg_init_uV;
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};
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#define clk_hw_to_dfll(_hw) container_of(_hw, struct tegra_dfll, dfll_clk_hw)
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@ -489,6 +505,34 @@ static void dfll_set_mode(struct tegra_dfll *td,
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dfll_wmb(td);
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}
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/*
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* DVCO rate control
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*/
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static unsigned long get_dvco_rate_below(struct tegra_dfll *td, u8 out_min)
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{
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struct dev_pm_opp *opp;
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unsigned long rate, prev_rate;
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unsigned long uv, min_uv;
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min_uv = td->lut_uv[out_min];
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for (rate = 0, prev_rate = 0; ; rate++) {
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opp = dev_pm_opp_find_freq_ceil(td->soc->dev, &rate);
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if (IS_ERR(opp))
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break;
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uv = dev_pm_opp_get_voltage(opp);
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dev_pm_opp_put(opp);
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if (uv && uv > min_uv)
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return prev_rate;
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prev_rate = rate;
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}
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return prev_rate;
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}
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/*
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* DFLL-to-I2C controller interface
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*/
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@ -518,6 +562,118 @@ static int dfll_i2c_set_output_enabled(struct tegra_dfll *td, bool enable)
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return 0;
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}
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/*
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* DFLL-to-PWM controller interface
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*/
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/**
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* dfll_pwm_set_output_enabled - enable/disable PWM voltage requests
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* @td: DFLL instance
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* @enable: whether to enable or disable the PWM voltage requests
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*
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* Set the master enable control for PWM control value updates. If disabled,
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* then the PWM signal is not driven. Also configure the PWM output pad
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* to the appropriate state.
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*/
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static int dfll_pwm_set_output_enabled(struct tegra_dfll *td, bool enable)
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{
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int ret;
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u32 val, div;
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if (enable) {
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ret = pinctrl_select_state(td->pwm_pin, td->pwm_enable_state);
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if (ret < 0) {
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dev_err(td->dev, "setting enable state failed\n");
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return -EINVAL;
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}
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val = dfll_readl(td, DFLL_OUTPUT_CFG);
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val &= ~DFLL_OUTPUT_CFG_PWM_DIV_MASK;
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div = DIV_ROUND_UP(td->ref_rate, td->pwm_rate);
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val |= (div << DFLL_OUTPUT_CFG_PWM_DIV_SHIFT)
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& DFLL_OUTPUT_CFG_PWM_DIV_MASK;
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dfll_writel(td, val, DFLL_OUTPUT_CFG);
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dfll_wmb(td);
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val |= DFLL_OUTPUT_CFG_PWM_ENABLE;
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dfll_writel(td, val, DFLL_OUTPUT_CFG);
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dfll_wmb(td);
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} else {
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ret = pinctrl_select_state(td->pwm_pin, td->pwm_disable_state);
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if (ret < 0)
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dev_warn(td->dev, "setting disable state failed\n");
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val = dfll_readl(td, DFLL_OUTPUT_CFG);
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val &= ~DFLL_OUTPUT_CFG_PWM_ENABLE;
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dfll_writel(td, val, DFLL_OUTPUT_CFG);
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dfll_wmb(td);
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}
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return 0;
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}
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/**
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* dfll_set_force_output_value - set fixed value for force output
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* @td: DFLL instance
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* @out_val: value to force output
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*
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* Set the fixed value for force output, DFLL will output this value when
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* force output is enabled.
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*/
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static u32 dfll_set_force_output_value(struct tegra_dfll *td, u8 out_val)
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{
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u32 val = dfll_readl(td, DFLL_OUTPUT_FORCE);
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val = (val & DFLL_OUTPUT_FORCE_ENABLE) | (out_val & OUT_MASK);
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dfll_writel(td, val, DFLL_OUTPUT_FORCE);
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dfll_wmb(td);
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return dfll_readl(td, DFLL_OUTPUT_FORCE);
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}
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/**
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* dfll_set_force_output_enabled - enable/disable force output
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* @td: DFLL instance
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* @enable: whether to enable or disable the force output
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*
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* Set the enable control for fouce output with fixed value.
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*/
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static void dfll_set_force_output_enabled(struct tegra_dfll *td, bool enable)
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{
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u32 val = dfll_readl(td, DFLL_OUTPUT_FORCE);
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if (enable)
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val |= DFLL_OUTPUT_FORCE_ENABLE;
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else
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val &= ~DFLL_OUTPUT_FORCE_ENABLE;
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dfll_writel(td, val, DFLL_OUTPUT_FORCE);
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dfll_wmb(td);
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}
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/**
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* dfll_force_output - force output a fixed value
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* @td: DFLL instance
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* @out_sel: value to force output
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*
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* Set the fixed value for force output, DFLL will output this value.
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*/
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static int dfll_force_output(struct tegra_dfll *td, unsigned int out_sel)
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{
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u32 val;
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if (out_sel > OUT_MASK)
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return -EINVAL;
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val = dfll_set_force_output_value(td, out_sel);
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if ((td->mode < DFLL_CLOSED_LOOP) &&
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!(val & DFLL_OUTPUT_FORCE_ENABLE)) {
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dfll_set_force_output_enabled(td, true);
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}
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return 0;
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}
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/**
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* dfll_load_lut - load the voltage lookup table
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* @td: struct tegra_dfll *
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@ -539,7 +695,7 @@ static void dfll_load_i2c_lut(struct tegra_dfll *td)
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lut_index = i;
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val = regulator_list_hardware_vsel(td->vdd_reg,
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td->i2c_lut[lut_index]);
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td->lut[lut_index]);
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__raw_writel(val, td->lut_base + i * 4);
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}
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@ -594,24 +750,41 @@ static void dfll_init_out_if(struct tegra_dfll *td)
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{
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u32 val;
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td->lut_min = 0;
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td->lut_max = td->i2c_lut_size - 1;
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td->lut_safe = td->lut_min + 1;
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td->lut_min = td->lut_bottom;
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td->lut_max = td->lut_size - 1;
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td->lut_safe = td->lut_min + (td->lut_min < td->lut_max ? 1 : 0);
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/* clear DFLL_OUTPUT_CFG before setting new value */
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dfll_writel(td, 0, DFLL_OUTPUT_CFG);
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dfll_wmb(td);
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dfll_i2c_writel(td, 0, DFLL_OUTPUT_CFG);
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val = (td->lut_safe << DFLL_OUTPUT_CFG_SAFE_SHIFT) |
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(td->lut_max << DFLL_OUTPUT_CFG_MAX_SHIFT) |
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(td->lut_min << DFLL_OUTPUT_CFG_MIN_SHIFT);
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dfll_i2c_writel(td, val, DFLL_OUTPUT_CFG);
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dfll_i2c_wmb(td);
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(td->lut_max << DFLL_OUTPUT_CFG_MAX_SHIFT) |
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(td->lut_min << DFLL_OUTPUT_CFG_MIN_SHIFT);
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dfll_writel(td, val, DFLL_OUTPUT_CFG);
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dfll_wmb(td);
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dfll_writel(td, 0, DFLL_OUTPUT_FORCE);
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dfll_i2c_writel(td, 0, DFLL_INTR_EN);
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dfll_i2c_writel(td, DFLL_INTR_MAX_MASK | DFLL_INTR_MIN_MASK,
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DFLL_INTR_STS);
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dfll_load_i2c_lut(td);
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dfll_init_i2c_if(td);
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if (td->pmu_if == TEGRA_DFLL_PMU_PWM) {
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u32 vinit = td->reg_init_uV;
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int vstep = td->soc->alignment.step_uv;
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unsigned long vmin = td->lut_uv[0];
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/* set initial voltage */
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if ((vinit >= vmin) && vstep) {
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unsigned int vsel;
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vsel = DIV_ROUND_UP((vinit - vmin), vstep);
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dfll_force_output(td, vsel);
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}
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} else {
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dfll_load_i2c_lut(td);
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dfll_init_i2c_if(td);
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}
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}
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/*
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@ -631,17 +804,17 @@ static void dfll_init_out_if(struct tegra_dfll *td)
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static int find_lut_index_for_rate(struct tegra_dfll *td, unsigned long rate)
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{
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struct dev_pm_opp *opp;
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int i, uv;
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int i, align_step;
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opp = dev_pm_opp_find_freq_ceil(td->soc->dev, &rate);
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if (IS_ERR(opp))
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return PTR_ERR(opp);
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uv = dev_pm_opp_get_voltage(opp);
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align_step = dev_pm_opp_get_voltage(opp) / td->soc->alignment.step_uv;
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dev_pm_opp_put(opp);
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for (i = 0; i < td->i2c_lut_size; i++) {
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if (regulator_list_voltage(td->vdd_reg, td->i2c_lut[i]) == uv)
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for (i = td->lut_bottom; i < td->lut_size; i++) {
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if ((td->lut_uv[i] / td->soc->alignment.step_uv) >= align_step)
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return i;
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}
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@ -863,9 +1036,14 @@ static int dfll_lock(struct tegra_dfll *td)
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return -EINVAL;
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}
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dfll_i2c_set_output_enabled(td, true);
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if (td->pmu_if == TEGRA_DFLL_PMU_PWM)
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dfll_pwm_set_output_enabled(td, true);
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else
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dfll_i2c_set_output_enabled(td, true);
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dfll_set_mode(td, DFLL_CLOSED_LOOP);
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dfll_set_frequency_request(td, req);
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dfll_set_force_output_enabled(td, false);
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return 0;
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default:
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@ -889,7 +1067,10 @@ static int dfll_unlock(struct tegra_dfll *td)
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case DFLL_CLOSED_LOOP:
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dfll_set_open_loop_config(td);
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dfll_set_mode(td, DFLL_OPEN_LOOP);
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dfll_i2c_set_output_enabled(td, false);
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if (td->pmu_if == TEGRA_DFLL_PMU_PWM)
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dfll_pwm_set_output_enabled(td, false);
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else
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dfll_i2c_set_output_enabled(td, false);
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return 0;
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case DFLL_OPEN_LOOP:
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@ -1171,15 +1352,17 @@ static int attr_registers_show(struct seq_file *s, void *data)
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seq_printf(s, "[0x%02x] = 0x%08x\n", offs,
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dfll_i2c_readl(td, offs));
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seq_puts(s, "\nINTEGRATED I2C CONTROLLER REGISTERS:\n");
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offs = DFLL_I2C_CLK_DIVISOR;
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seq_printf(s, "[0x%02x] = 0x%08x\n", offs,
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__raw_readl(td->i2c_controller_base + offs));
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seq_puts(s, "\nLUT:\n");
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for (offs = 0; offs < 4 * MAX_DFLL_VOLTAGES; offs += 4)
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if (td->pmu_if == TEGRA_DFLL_PMU_I2C) {
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seq_puts(s, "\nINTEGRATED I2C CONTROLLER REGISTERS:\n");
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offs = DFLL_I2C_CLK_DIVISOR;
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seq_printf(s, "[0x%02x] = 0x%08x\n", offs,
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__raw_readl(td->lut_base + offs));
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__raw_readl(td->i2c_controller_base + offs));
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seq_puts(s, "\nLUT:\n");
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for (offs = 0; offs < 4 * MAX_DFLL_VOLTAGES; offs += 4)
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seq_printf(s, "[0x%02x] = 0x%08x\n", offs,
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__raw_readl(td->lut_base + offs));
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}
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return 0;
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}
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@ -1349,15 +1532,21 @@ static int dfll_init(struct tegra_dfll *td)
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*/
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static int find_vdd_map_entry_exact(struct tegra_dfll *td, int uV)
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{
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int i, n_voltages, reg_uV;
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int i, n_voltages, reg_uV,reg_volt_id, align_step;
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if (WARN_ON(td->pmu_if == TEGRA_DFLL_PMU_PWM))
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return -EINVAL;
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align_step = uV / td->soc->alignment.step_uv;
|
||||
n_voltages = regulator_count_voltages(td->vdd_reg);
|
||||
for (i = 0; i < n_voltages; i++) {
|
||||
reg_uV = regulator_list_voltage(td->vdd_reg, i);
|
||||
if (reg_uV < 0)
|
||||
break;
|
||||
|
||||
if (uV == reg_uV)
|
||||
reg_volt_id = reg_uV / td->soc->alignment.step_uv;
|
||||
|
||||
if (align_step == reg_volt_id)
|
||||
return i;
|
||||
}
|
||||
|
||||
|
|
@ -1371,15 +1560,21 @@ static int find_vdd_map_entry_exact(struct tegra_dfll *td, int uV)
|
|||
* */
|
||||
static int find_vdd_map_entry_min(struct tegra_dfll *td, int uV)
|
||||
{
|
||||
int i, n_voltages, reg_uV;
|
||||
int i, n_voltages, reg_uV, reg_volt_id, align_step;
|
||||
|
||||
if (WARN_ON(td->pmu_if == TEGRA_DFLL_PMU_PWM))
|
||||
return -EINVAL;
|
||||
|
||||
align_step = uV / td->soc->alignment.step_uv;
|
||||
n_voltages = regulator_count_voltages(td->vdd_reg);
|
||||
for (i = 0; i < n_voltages; i++) {
|
||||
reg_uV = regulator_list_voltage(td->vdd_reg, i);
|
||||
if (reg_uV < 0)
|
||||
break;
|
||||
|
||||
if (uV <= reg_uV)
|
||||
reg_volt_id = reg_uV / td->soc->alignment.step_uv;
|
||||
|
||||
if (align_step <= reg_volt_id)
|
||||
return i;
|
||||
}
|
||||
|
||||
|
|
@ -1387,9 +1582,61 @@ static int find_vdd_map_entry_min(struct tegra_dfll *td, int uV)
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
/*
|
||||
* dfll_build_pwm_lut - build the PWM regulator lookup table
|
||||
* @td: DFLL instance
|
||||
* @v_max: Vmax from OPP table
|
||||
*
|
||||
* Look-up table in h/w is ignored when PWM is used as DFLL interface to PMIC.
|
||||
* In this case closed loop output is controlling duty cycle directly. The s/w
|
||||
* look-up that maps PWM duty cycle to voltage is still built by this function.
|
||||
*/
|
||||
static int dfll_build_pwm_lut(struct tegra_dfll *td, unsigned long v_max)
|
||||
{
|
||||
int i;
|
||||
unsigned long rate, reg_volt;
|
||||
u8 lut_bottom = MAX_DFLL_VOLTAGES;
|
||||
int v_min = td->soc->cvb->min_millivolts * 1000;
|
||||
|
||||
for (i = 0; i < MAX_DFLL_VOLTAGES; i++) {
|
||||
reg_volt = td->lut_uv[i];
|
||||
|
||||
/* since opp voltage is exact mv */
|
||||
reg_volt = (reg_volt / 1000) * 1000;
|
||||
if (reg_volt > v_max)
|
||||
break;
|
||||
|
||||
td->lut[i] = i;
|
||||
if ((lut_bottom == MAX_DFLL_VOLTAGES) && (reg_volt >= v_min))
|
||||
lut_bottom = i;
|
||||
}
|
||||
|
||||
/* determine voltage boundaries */
|
||||
td->lut_size = i;
|
||||
if ((lut_bottom == MAX_DFLL_VOLTAGES) ||
|
||||
(lut_bottom + 1 >= td->lut_size)) {
|
||||
dev_err(td->dev, "no voltage above DFLL minimum %d mV\n",
|
||||
td->soc->cvb->min_millivolts);
|
||||
return -EINVAL;
|
||||
}
|
||||
td->lut_bottom = lut_bottom;
|
||||
|
||||
/* determine rate boundaries */
|
||||
rate = get_dvco_rate_below(td, td->lut_bottom);
|
||||
if (!rate) {
|
||||
dev_err(td->dev, "no opp below DFLL minimum voltage %d mV\n",
|
||||
td->soc->cvb->min_millivolts);
|
||||
return -EINVAL;
|
||||
}
|
||||
td->dvco_rate_min = rate;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* dfll_build_i2c_lut - build the I2C voltage register lookup table
|
||||
* @td: DFLL instance
|
||||
* @v_max: Vmax from OPP table
|
||||
*
|
||||
* The DFLL hardware has 33 bytes of look-up table RAM that must be filled with
|
||||
* PMIC voltage register values that span the entire DFLL operating range.
|
||||
|
|
@ -1397,33 +1644,24 @@ static int find_vdd_map_entry_min(struct tegra_dfll *td, int uV)
|
|||
* the soc-specific platform driver (td->soc->opp_dev) and the PMIC
|
||||
* register-to-voltage mapping queried from the regulator framework.
|
||||
*
|
||||
* On success, fills in td->i2c_lut and returns 0, or -err on failure.
|
||||
* On success, fills in td->lut and returns 0, or -err on failure.
|
||||
*/
|
||||
static int dfll_build_i2c_lut(struct tegra_dfll *td)
|
||||
static int dfll_build_i2c_lut(struct tegra_dfll *td, unsigned long v_max)
|
||||
{
|
||||
unsigned long rate, v, v_opp;
|
||||
int ret = -EINVAL;
|
||||
int j, v, v_max, v_opp;
|
||||
int selector;
|
||||
unsigned long rate;
|
||||
struct dev_pm_opp *opp;
|
||||
int lut;
|
||||
|
||||
rate = ULONG_MAX;
|
||||
opp = dev_pm_opp_find_freq_floor(td->soc->dev, &rate);
|
||||
if (IS_ERR(opp)) {
|
||||
dev_err(td->dev, "couldn't get vmax opp, empty opp table?\n");
|
||||
goto out;
|
||||
}
|
||||
v_max = dev_pm_opp_get_voltage(opp);
|
||||
dev_pm_opp_put(opp);
|
||||
int j, selector, lut;
|
||||
|
||||
v = td->soc->cvb->min_millivolts * 1000;
|
||||
lut = find_vdd_map_entry_exact(td, v);
|
||||
if (lut < 0)
|
||||
goto out;
|
||||
td->i2c_lut[0] = lut;
|
||||
td->lut[0] = lut;
|
||||
td->lut_bottom = 0;
|
||||
|
||||
for (j = 1, rate = 0; ; rate++) {
|
||||
struct dev_pm_opp *opp;
|
||||
|
||||
opp = dev_pm_opp_find_freq_ceil(td->soc->dev, &rate);
|
||||
if (IS_ERR(opp))
|
||||
break;
|
||||
|
|
@ -1435,39 +1673,64 @@ static int dfll_build_i2c_lut(struct tegra_dfll *td)
|
|||
dev_pm_opp_put(opp);
|
||||
|
||||
for (;;) {
|
||||
v += max(1, (v_max - v) / (MAX_DFLL_VOLTAGES - j));
|
||||
v += max(1UL, (v_max - v) / (MAX_DFLL_VOLTAGES - j));
|
||||
if (v >= v_opp)
|
||||
break;
|
||||
|
||||
selector = find_vdd_map_entry_min(td, v);
|
||||
if (selector < 0)
|
||||
goto out;
|
||||
if (selector != td->i2c_lut[j - 1])
|
||||
td->i2c_lut[j++] = selector;
|
||||
if (selector != td->lut[j - 1])
|
||||
td->lut[j++] = selector;
|
||||
}
|
||||
|
||||
v = (j == MAX_DFLL_VOLTAGES - 1) ? v_max : v_opp;
|
||||
selector = find_vdd_map_entry_exact(td, v);
|
||||
if (selector < 0)
|
||||
goto out;
|
||||
if (selector != td->i2c_lut[j - 1])
|
||||
td->i2c_lut[j++] = selector;
|
||||
if (selector != td->lut[j - 1])
|
||||
td->lut[j++] = selector;
|
||||
|
||||
if (v >= v_max)
|
||||
break;
|
||||
}
|
||||
td->i2c_lut_size = j;
|
||||
td->lut_size = j;
|
||||
|
||||
if (!td->dvco_rate_min)
|
||||
dev_err(td->dev, "no opp above DFLL minimum voltage %d mV\n",
|
||||
td->soc->cvb->min_millivolts);
|
||||
else
|
||||
else {
|
||||
ret = 0;
|
||||
for (j = 0; j < td->lut_size; j++)
|
||||
td->lut_uv[j] =
|
||||
regulator_list_voltage(td->vdd_reg,
|
||||
td->lut[j]);
|
||||
}
|
||||
|
||||
out:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int dfll_build_lut(struct tegra_dfll *td)
|
||||
{
|
||||
unsigned long rate, v_max;
|
||||
struct dev_pm_opp *opp;
|
||||
|
||||
rate = ULONG_MAX;
|
||||
opp = dev_pm_opp_find_freq_floor(td->soc->dev, &rate);
|
||||
if (IS_ERR(opp)) {
|
||||
dev_err(td->dev, "couldn't get vmax opp, empty opp table?\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
v_max = dev_pm_opp_get_voltage(opp);
|
||||
dev_pm_opp_put(opp);
|
||||
|
||||
if (td->pmu_if == TEGRA_DFLL_PMU_PWM)
|
||||
return dfll_build_pwm_lut(td, v_max);
|
||||
else
|
||||
return dfll_build_i2c_lut(td, v_max);
|
||||
}
|
||||
|
||||
/**
|
||||
* read_dt_param - helper function for reading required parameters from the DT
|
||||
* @td: DFLL instance
|
||||
|
|
@ -1526,12 +1789,57 @@ static int dfll_fetch_i2c_params(struct tegra_dfll *td)
|
|||
}
|
||||
td->i2c_reg = vsel_reg;
|
||||
|
||||
ret = dfll_build_i2c_lut(td);
|
||||
if (ret) {
|
||||
dev_err(td->dev, "couldn't build I2C LUT\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int dfll_fetch_pwm_params(struct tegra_dfll *td)
|
||||
{
|
||||
int ret, i;
|
||||
u32 pwm_period;
|
||||
|
||||
if (!td->soc->alignment.step_uv || !td->soc->alignment.offset_uv) {
|
||||
dev_err(td->dev,
|
||||
"Missing step or alignment info for PWM regulator");
|
||||
return -EINVAL;
|
||||
}
|
||||
for (i = 0; i < MAX_DFLL_VOLTAGES; i++)
|
||||
td->lut_uv[i] = td->soc->alignment.offset_uv +
|
||||
i * td->soc->alignment.step_uv;
|
||||
|
||||
ret = read_dt_param(td, "nvidia,pwm-tristate-microvolts",
|
||||
&td->reg_init_uV);
|
||||
if (!ret) {
|
||||
dev_err(td->dev, "couldn't get initialized voltage\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = read_dt_param(td, "nvidia,pwm-period-nanoseconds", &pwm_period);
|
||||
if (!ret) {
|
||||
dev_err(td->dev, "couldn't get PWM period\n");
|
||||
return ret;
|
||||
}
|
||||
td->pwm_rate = (NSEC_PER_SEC / pwm_period) * (MAX_DFLL_VOLTAGES - 1);
|
||||
|
||||
td->pwm_pin = devm_pinctrl_get(td->dev);
|
||||
if (IS_ERR(td->pwm_pin)) {
|
||||
dev_err(td->dev, "DT: missing pinctrl device\n");
|
||||
return PTR_ERR(td->pwm_pin);
|
||||
}
|
||||
|
||||
td->pwm_enable_state = pinctrl_lookup_state(td->pwm_pin,
|
||||
"dvfs_pwm_enable");
|
||||
if (IS_ERR(td->pwm_enable_state)) {
|
||||
dev_err(td->dev, "DT: missing pwm enabled state\n");
|
||||
return PTR_ERR(td->pwm_enable_state);
|
||||
}
|
||||
|
||||
td->pwm_disable_state = pinctrl_lookup_state(td->pwm_pin,
|
||||
"dvfs_pwm_disable");
|
||||
if (IS_ERR(td->pwm_disable_state)) {
|
||||
dev_err(td->dev, "DT: missing pwm disabled state\n");
|
||||
return PTR_ERR(td->pwm_disable_state);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -1597,16 +1905,6 @@ int tegra_dfll_register(struct platform_device *pdev,
|
|||
|
||||
td->soc = soc;
|
||||
|
||||
td->vdd_reg = devm_regulator_get(td->dev, "vdd-cpu");
|
||||
if (IS_ERR(td->vdd_reg)) {
|
||||
ret = PTR_ERR(td->vdd_reg);
|
||||
if (ret != -EPROBE_DEFER)
|
||||
dev_err(td->dev, "couldn't get vdd_cpu regulator: %d\n",
|
||||
ret);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
td->dvco_rst = devm_reset_control_get(td->dev, "dvco");
|
||||
if (IS_ERR(td->dvco_rst)) {
|
||||
dev_err(td->dev, "couldn't get dvco reset\n");
|
||||
|
|
@ -1619,10 +1917,27 @@ int tegra_dfll_register(struct platform_device *pdev,
|
|||
return ret;
|
||||
}
|
||||
|
||||
ret = dfll_fetch_i2c_params(td);
|
||||
if (of_property_read_bool(td->dev->of_node, "nvidia,pwm-to-pmic")) {
|
||||
td->pmu_if = TEGRA_DFLL_PMU_PWM;
|
||||
ret = dfll_fetch_pwm_params(td);
|
||||
} else {
|
||||
td->vdd_reg = devm_regulator_get(td->dev, "vdd-cpu");
|
||||
if (IS_ERR(td->vdd_reg)) {
|
||||
dev_err(td->dev, "couldn't get vdd_cpu regulator\n");
|
||||
return PTR_ERR(td->vdd_reg);
|
||||
}
|
||||
td->pmu_if = TEGRA_DFLL_PMU_I2C;
|
||||
ret = dfll_fetch_i2c_params(td);
|
||||
}
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = dfll_build_lut(td);
|
||||
if (ret) {
|
||||
dev_err(td->dev, "couldn't build LUT\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (!mem) {
|
||||
dev_err(td->dev, "no control register resource\n");
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
/*
|
||||
* clk-dfll.h - prototypes and macros for the Tegra DFLL clocksource driver
|
||||
* Copyright (C) 2013 NVIDIA Corporation. All rights reserved.
|
||||
* Copyright (C) 2013-2019 NVIDIA Corporation. All rights reserved.
|
||||
*
|
||||
* Aleksandr Frid <afrid@nvidia.com>
|
||||
* Paul Walmsley <pwalmsley@nvidia.com>
|
||||
|
|
@ -22,11 +22,14 @@
|
|||
#include <linux/reset.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
#include "cvb.h"
|
||||
|
||||
/**
|
||||
* struct tegra_dfll_soc_data - SoC-specific hooks/integration for the DFLL driver
|
||||
* @dev: struct device * that holds the OPP table for the DFLL
|
||||
* @max_freq: maximum frequency supported on this SoC
|
||||
* @cvb: CPU frequency table for this SoC
|
||||
* @alignment: parameters of the regulator step and offset
|
||||
* @init_clock_trimmers: callback to initialize clock trimmers
|
||||
* @set_clock_trimmers_high: callback to tune clock trimmers for high voltage
|
||||
* @set_clock_trimmers_low: callback to tune clock trimmers for low voltage
|
||||
|
|
@ -35,6 +38,7 @@ struct tegra_dfll_soc_data {
|
|||
struct device *dev;
|
||||
unsigned long max_freq;
|
||||
const struct cvb_table *cvb;
|
||||
struct rail_alignment alignment;
|
||||
|
||||
void (*init_clock_trimmers)(void);
|
||||
void (*set_clock_trimmers_high)(void);
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* Tegra124 DFLL FCPU clock source driver
|
||||
*
|
||||
* Copyright (C) 2012-2014 NVIDIA Corporation. All rights reserved.
|
||||
* Copyright (C) 2012-2019 NVIDIA Corporation. All rights reserved.
|
||||
*
|
||||
* Aleksandr Frid <afrid@nvidia.com>
|
||||
* Paul Walmsley <pwalmsley@nvidia.com>
|
||||
|
|
@ -21,15 +21,24 @@
|
|||
#include <linux/err.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/regulator/consumer.h>
|
||||
#include <soc/tegra/fuse.h>
|
||||
|
||||
#include "clk.h"
|
||||
#include "clk-dfll.h"
|
||||
#include "cvb.h"
|
||||
|
||||
struct dfll_fcpu_data {
|
||||
const unsigned long *cpu_max_freq_table;
|
||||
unsigned int cpu_max_freq_table_size;
|
||||
const struct cvb_table *cpu_cvb_tables;
|
||||
unsigned int cpu_cvb_tables_size;
|
||||
};
|
||||
|
||||
/* Maximum CPU frequency, indexed by CPU speedo id */
|
||||
static const unsigned long cpu_max_freq_table[] = {
|
||||
static const unsigned long tegra124_cpu_max_freq_table[] = {
|
||||
[0] = 2014500000UL,
|
||||
[1] = 2320500000UL,
|
||||
[2] = 2116500000UL,
|
||||
|
|
@ -42,9 +51,6 @@ static const struct cvb_table tegra124_cpu_cvb_tables[] = {
|
|||
.process_id = -1,
|
||||
.min_millivolts = 900,
|
||||
.max_millivolts = 1260,
|
||||
.alignment = {
|
||||
.step_uv = 10000, /* 10mV */
|
||||
},
|
||||
.speedo_scale = 100,
|
||||
.voltage_scale = 1000,
|
||||
.entries = {
|
||||
|
|
@ -82,16 +88,493 @@ static const struct cvb_table tegra124_cpu_cvb_tables[] = {
|
|||
},
|
||||
};
|
||||
|
||||
static const unsigned long tegra210_cpu_max_freq_table[] = {
|
||||
[0] = 1912500000UL,
|
||||
[1] = 1912500000UL,
|
||||
[2] = 2218500000UL,
|
||||
[3] = 1785000000UL,
|
||||
[4] = 1632000000UL,
|
||||
[5] = 1912500000UL,
|
||||
[6] = 2014500000UL,
|
||||
[7] = 1734000000UL,
|
||||
[8] = 1683000000UL,
|
||||
[9] = 1555500000UL,
|
||||
[10] = 1504500000UL,
|
||||
};
|
||||
|
||||
#define CPU_CVB_TABLE \
|
||||
.speedo_scale = 100, \
|
||||
.voltage_scale = 1000, \
|
||||
.entries = { \
|
||||
{ 204000000UL, { 1007452, -23865, 370 } }, \
|
||||
{ 306000000UL, { 1052709, -24875, 370 } }, \
|
||||
{ 408000000UL, { 1099069, -25895, 370 } }, \
|
||||
{ 510000000UL, { 1146534, -26905, 370 } }, \
|
||||
{ 612000000UL, { 1195102, -27915, 370 } }, \
|
||||
{ 714000000UL, { 1244773, -28925, 370 } }, \
|
||||
{ 816000000UL, { 1295549, -29935, 370 } }, \
|
||||
{ 918000000UL, { 1347428, -30955, 370 } }, \
|
||||
{ 1020000000UL, { 1400411, -31965, 370 } }, \
|
||||
{ 1122000000UL, { 1454497, -32975, 370 } }, \
|
||||
{ 1224000000UL, { 1509687, -33985, 370 } }, \
|
||||
{ 1326000000UL, { 1565981, -35005, 370 } }, \
|
||||
{ 1428000000UL, { 1623379, -36015, 370 } }, \
|
||||
{ 1530000000UL, { 1681880, -37025, 370 } }, \
|
||||
{ 1632000000UL, { 1741485, -38035, 370 } }, \
|
||||
{ 1734000000UL, { 1802194, -39055, 370 } }, \
|
||||
{ 1836000000UL, { 1864006, -40065, 370 } }, \
|
||||
{ 1912500000UL, { 1910780, -40815, 370 } }, \
|
||||
{ 2014500000UL, { 1227000, 0, 0 } }, \
|
||||
{ 2218500000UL, { 1227000, 0, 0 } }, \
|
||||
{ 0UL, { 0, 0, 0 } }, \
|
||||
}
|
||||
|
||||
#define CPU_CVB_TABLE_XA \
|
||||
.speedo_scale = 100, \
|
||||
.voltage_scale = 1000, \
|
||||
.entries = { \
|
||||
{ 204000000UL, { 1250024, -39785, 565 } }, \
|
||||
{ 306000000UL, { 1297556, -41145, 565 } }, \
|
||||
{ 408000000UL, { 1346718, -42505, 565 } }, \
|
||||
{ 510000000UL, { 1397511, -43855, 565 } }, \
|
||||
{ 612000000UL, { 1449933, -45215, 565 } }, \
|
||||
{ 714000000UL, { 1503986, -46575, 565 } }, \
|
||||
{ 816000000UL, { 1559669, -47935, 565 } }, \
|
||||
{ 918000000UL, { 1616982, -49295, 565 } }, \
|
||||
{ 1020000000UL, { 1675926, -50645, 565 } }, \
|
||||
{ 1122000000UL, { 1736500, -52005, 565 } }, \
|
||||
{ 1224000000UL, { 1798704, -53365, 565 } }, \
|
||||
{ 1326000000UL, { 1862538, -54725, 565 } }, \
|
||||
{ 1428000000UL, { 1928003, -56085, 565 } }, \
|
||||
{ 1530000000UL, { 1995097, -57435, 565 } }, \
|
||||
{ 1606500000UL, { 2046149, -58445, 565 } }, \
|
||||
{ 1632000000UL, { 2063822, -58795, 565 } }, \
|
||||
{ 0UL, { 0, 0, 0 } }, \
|
||||
}
|
||||
|
||||
#define CPU_CVB_TABLE_EUCM1 \
|
||||
.speedo_scale = 100, \
|
||||
.voltage_scale = 1000, \
|
||||
.entries = { \
|
||||
{ 204000000UL, { 734429, 0, 0 } }, \
|
||||
{ 306000000UL, { 768191, 0, 0 } }, \
|
||||
{ 408000000UL, { 801953, 0, 0 } }, \
|
||||
{ 510000000UL, { 835715, 0, 0 } }, \
|
||||
{ 612000000UL, { 869477, 0, 0 } }, \
|
||||
{ 714000000UL, { 903239, 0, 0 } }, \
|
||||
{ 816000000UL, { 937001, 0, 0 } }, \
|
||||
{ 918000000UL, { 970763, 0, 0 } }, \
|
||||
{ 1020000000UL, { 1004525, 0, 0 } }, \
|
||||
{ 1122000000UL, { 1038287, 0, 0 } }, \
|
||||
{ 1224000000UL, { 1072049, 0, 0 } }, \
|
||||
{ 1326000000UL, { 1105811, 0, 0 } }, \
|
||||
{ 1428000000UL, { 1130000, 0, 0 } }, \
|
||||
{ 1555500000UL, { 1130000, 0, 0 } }, \
|
||||
{ 1632000000UL, { 1170000, 0, 0 } }, \
|
||||
{ 1734000000UL, { 1227500, 0, 0 } }, \
|
||||
{ 0UL, { 0, 0, 0 } }, \
|
||||
}
|
||||
|
||||
#define CPU_CVB_TABLE_EUCM2 \
|
||||
.speedo_scale = 100, \
|
||||
.voltage_scale = 1000, \
|
||||
.entries = { \
|
||||
{ 204000000UL, { 742283, 0, 0 } }, \
|
||||
{ 306000000UL, { 776249, 0, 0 } }, \
|
||||
{ 408000000UL, { 810215, 0, 0 } }, \
|
||||
{ 510000000UL, { 844181, 0, 0 } }, \
|
||||
{ 612000000UL, { 878147, 0, 0 } }, \
|
||||
{ 714000000UL, { 912113, 0, 0 } }, \
|
||||
{ 816000000UL, { 946079, 0, 0 } }, \
|
||||
{ 918000000UL, { 980045, 0, 0 } }, \
|
||||
{ 1020000000UL, { 1014011, 0, 0 } }, \
|
||||
{ 1122000000UL, { 1047977, 0, 0 } }, \
|
||||
{ 1224000000UL, { 1081943, 0, 0 } }, \
|
||||
{ 1326000000UL, { 1090000, 0, 0 } }, \
|
||||
{ 1479000000UL, { 1090000, 0, 0 } }, \
|
||||
{ 1555500000UL, { 1162000, 0, 0 } }, \
|
||||
{ 1683000000UL, { 1195000, 0, 0 } }, \
|
||||
{ 0UL, { 0, 0, 0 } }, \
|
||||
}
|
||||
|
||||
#define CPU_CVB_TABLE_EUCM2_JOINT_RAIL \
|
||||
.speedo_scale = 100, \
|
||||
.voltage_scale = 1000, \
|
||||
.entries = { \
|
||||
{ 204000000UL, { 742283, 0, 0 } }, \
|
||||
{ 306000000UL, { 776249, 0, 0 } }, \
|
||||
{ 408000000UL, { 810215, 0, 0 } }, \
|
||||
{ 510000000UL, { 844181, 0, 0 } }, \
|
||||
{ 612000000UL, { 878147, 0, 0 } }, \
|
||||
{ 714000000UL, { 912113, 0, 0 } }, \
|
||||
{ 816000000UL, { 946079, 0, 0 } }, \
|
||||
{ 918000000UL, { 980045, 0, 0 } }, \
|
||||
{ 1020000000UL, { 1014011, 0, 0 } }, \
|
||||
{ 1122000000UL, { 1047977, 0, 0 } }, \
|
||||
{ 1224000000UL, { 1081943, 0, 0 } }, \
|
||||
{ 1326000000UL, { 1090000, 0, 0 } }, \
|
||||
{ 1479000000UL, { 1090000, 0, 0 } }, \
|
||||
{ 1504500000UL, { 1120000, 0, 0 } }, \
|
||||
{ 0UL, { 0, 0, 0 } }, \
|
||||
}
|
||||
|
||||
#define CPU_CVB_TABLE_ODN \
|
||||
.speedo_scale = 100, \
|
||||
.voltage_scale = 1000, \
|
||||
.entries = { \
|
||||
{ 204000000UL, { 721094, 0, 0 } }, \
|
||||
{ 306000000UL, { 754040, 0, 0 } }, \
|
||||
{ 408000000UL, { 786986, 0, 0 } }, \
|
||||
{ 510000000UL, { 819932, 0, 0 } }, \
|
||||
{ 612000000UL, { 852878, 0, 0 } }, \
|
||||
{ 714000000UL, { 885824, 0, 0 } }, \
|
||||
{ 816000000UL, { 918770, 0, 0 } }, \
|
||||
{ 918000000UL, { 915716, 0, 0 } }, \
|
||||
{ 1020000000UL, { 984662, 0, 0 } }, \
|
||||
{ 1122000000UL, { 1017608, 0, 0 } }, \
|
||||
{ 1224000000UL, { 1050554, 0, 0 } }, \
|
||||
{ 1326000000UL, { 1083500, 0, 0 } }, \
|
||||
{ 1428000000UL, { 1116446, 0, 0 } }, \
|
||||
{ 1581000000UL, { 1130000, 0, 0 } }, \
|
||||
{ 1683000000UL, { 1168000, 0, 0 } }, \
|
||||
{ 1785000000UL, { 1227500, 0, 0 } }, \
|
||||
{ 0UL, { 0, 0, 0 } }, \
|
||||
}
|
||||
|
||||
struct cvb_table tegra210_cpu_cvb_tables[] = {
|
||||
{
|
||||
.speedo_id = 10,
|
||||
.process_id = 0,
|
||||
.min_millivolts = 840,
|
||||
.max_millivolts = 1120,
|
||||
CPU_CVB_TABLE_EUCM2_JOINT_RAIL,
|
||||
.cpu_dfll_data = {
|
||||
.tune0_low = 0xffead0ff,
|
||||
.tune0_high = 0xffead0ff,
|
||||
.tune1 = 0x20091d9,
|
||||
.tune_high_min_millivolts = 864,
|
||||
}
|
||||
},
|
||||
{
|
||||
.speedo_id = 10,
|
||||
.process_id = 1,
|
||||
.min_millivolts = 840,
|
||||
.max_millivolts = 1120,
|
||||
CPU_CVB_TABLE_EUCM2_JOINT_RAIL,
|
||||
.cpu_dfll_data = {
|
||||
.tune0_low = 0xffead0ff,
|
||||
.tune0_high = 0xffead0ff,
|
||||
.tune1 = 0x20091d9,
|
||||
.tune_high_min_millivolts = 864,
|
||||
}
|
||||
},
|
||||
{
|
||||
.speedo_id = 9,
|
||||
.process_id = 0,
|
||||
.min_millivolts = 900,
|
||||
.max_millivolts = 1162,
|
||||
CPU_CVB_TABLE_EUCM2,
|
||||
.cpu_dfll_data = {
|
||||
.tune0_low = 0xffead0ff,
|
||||
.tune0_high = 0xffead0ff,
|
||||
.tune1 = 0x20091d9,
|
||||
}
|
||||
},
|
||||
{
|
||||
.speedo_id = 9,
|
||||
.process_id = 1,
|
||||
.min_millivolts = 900,
|
||||
.max_millivolts = 1162,
|
||||
CPU_CVB_TABLE_EUCM2,
|
||||
.cpu_dfll_data = {
|
||||
.tune0_low = 0xffead0ff,
|
||||
.tune0_high = 0xffead0ff,
|
||||
.tune1 = 0x20091d9,
|
||||
}
|
||||
},
|
||||
{
|
||||
.speedo_id = 8,
|
||||
.process_id = 0,
|
||||
.min_millivolts = 900,
|
||||
.max_millivolts = 1195,
|
||||
CPU_CVB_TABLE_EUCM2,
|
||||
.cpu_dfll_data = {
|
||||
.tune0_low = 0xffead0ff,
|
||||
.tune0_high = 0xffead0ff,
|
||||
.tune1 = 0x20091d9,
|
||||
}
|
||||
},
|
||||
{
|
||||
.speedo_id = 8,
|
||||
.process_id = 1,
|
||||
.min_millivolts = 900,
|
||||
.max_millivolts = 1195,
|
||||
CPU_CVB_TABLE_EUCM2,
|
||||
.cpu_dfll_data = {
|
||||
.tune0_low = 0xffead0ff,
|
||||
.tune0_high = 0xffead0ff,
|
||||
.tune1 = 0x20091d9,
|
||||
}
|
||||
},
|
||||
{
|
||||
.speedo_id = 7,
|
||||
.process_id = 0,
|
||||
.min_millivolts = 841,
|
||||
.max_millivolts = 1227,
|
||||
CPU_CVB_TABLE_EUCM1,
|
||||
.cpu_dfll_data = {
|
||||
.tune0_low = 0xffead0ff,
|
||||
.tune0_high = 0xffead0ff,
|
||||
.tune1 = 0x20091d9,
|
||||
.tune_high_min_millivolts = 864,
|
||||
}
|
||||
},
|
||||
{
|
||||
.speedo_id = 7,
|
||||
.process_id = 1,
|
||||
.min_millivolts = 841,
|
||||
.max_millivolts = 1227,
|
||||
CPU_CVB_TABLE_EUCM1,
|
||||
.cpu_dfll_data = {
|
||||
.tune0_low = 0xffead0ff,
|
||||
.tune0_high = 0xffead0ff,
|
||||
.tune1 = 0x20091d9,
|
||||
.tune_high_min_millivolts = 864,
|
||||
}
|
||||
},
|
||||
{
|
||||
.speedo_id = 6,
|
||||
.process_id = 0,
|
||||
.min_millivolts = 870,
|
||||
.max_millivolts = 1150,
|
||||
CPU_CVB_TABLE,
|
||||
.cpu_dfll_data = {
|
||||
.tune0_low = 0xffead0ff,
|
||||
.tune1 = 0x20091d9,
|
||||
}
|
||||
},
|
||||
{
|
||||
.speedo_id = 6,
|
||||
.process_id = 1,
|
||||
.min_millivolts = 870,
|
||||
.max_millivolts = 1150,
|
||||
CPU_CVB_TABLE,
|
||||
.cpu_dfll_data = {
|
||||
.tune0_low = 0xffead0ff,
|
||||
.tune1 = 0x25501d0,
|
||||
}
|
||||
},
|
||||
{
|
||||
.speedo_id = 5,
|
||||
.process_id = 0,
|
||||
.min_millivolts = 818,
|
||||
.max_millivolts = 1227,
|
||||
CPU_CVB_TABLE,
|
||||
.cpu_dfll_data = {
|
||||
.tune0_low = 0xffead0ff,
|
||||
.tune0_high = 0xffead0ff,
|
||||
.tune1 = 0x20091d9,
|
||||
.tune_high_min_millivolts = 864,
|
||||
}
|
||||
},
|
||||
{
|
||||
.speedo_id = 5,
|
||||
.process_id = 1,
|
||||
.min_millivolts = 818,
|
||||
.max_millivolts = 1227,
|
||||
CPU_CVB_TABLE,
|
||||
.cpu_dfll_data = {
|
||||
.tune0_low = 0xffead0ff,
|
||||
.tune0_high = 0xffead0ff,
|
||||
.tune1 = 0x25501d0,
|
||||
.tune_high_min_millivolts = 864,
|
||||
}
|
||||
},
|
||||
{
|
||||
.speedo_id = 4,
|
||||
.process_id = -1,
|
||||
.min_millivolts = 918,
|
||||
.max_millivolts = 1113,
|
||||
CPU_CVB_TABLE_XA,
|
||||
.cpu_dfll_data = {
|
||||
.tune0_low = 0xffead0ff,
|
||||
.tune1 = 0x17711BD,
|
||||
}
|
||||
},
|
||||
{
|
||||
.speedo_id = 3,
|
||||
.process_id = 0,
|
||||
.min_millivolts = 825,
|
||||
.max_millivolts = 1227,
|
||||
CPU_CVB_TABLE_ODN,
|
||||
.cpu_dfll_data = {
|
||||
.tune0_low = 0xffead0ff,
|
||||
.tune0_high = 0xffead0ff,
|
||||
.tune1 = 0x20091d9,
|
||||
.tune_high_min_millivolts = 864,
|
||||
}
|
||||
},
|
||||
{
|
||||
.speedo_id = 3,
|
||||
.process_id = 1,
|
||||
.min_millivolts = 825,
|
||||
.max_millivolts = 1227,
|
||||
CPU_CVB_TABLE_ODN,
|
||||
.cpu_dfll_data = {
|
||||
.tune0_low = 0xffead0ff,
|
||||
.tune0_high = 0xffead0ff,
|
||||
.tune1 = 0x25501d0,
|
||||
.tune_high_min_millivolts = 864,
|
||||
}
|
||||
},
|
||||
{
|
||||
.speedo_id = 2,
|
||||
.process_id = 0,
|
||||
.min_millivolts = 870,
|
||||
.max_millivolts = 1227,
|
||||
CPU_CVB_TABLE,
|
||||
.cpu_dfll_data = {
|
||||
.tune0_low = 0xffead0ff,
|
||||
.tune1 = 0x20091d9,
|
||||
}
|
||||
},
|
||||
{
|
||||
.speedo_id = 2,
|
||||
.process_id = 1,
|
||||
.min_millivolts = 870,
|
||||
.max_millivolts = 1227,
|
||||
CPU_CVB_TABLE,
|
||||
.cpu_dfll_data = {
|
||||
.tune0_low = 0xffead0ff,
|
||||
.tune1 = 0x25501d0,
|
||||
}
|
||||
},
|
||||
{
|
||||
.speedo_id = 1,
|
||||
.process_id = 0,
|
||||
.min_millivolts = 837,
|
||||
.max_millivolts = 1227,
|
||||
CPU_CVB_TABLE,
|
||||
.cpu_dfll_data = {
|
||||
.tune0_low = 0xffead0ff,
|
||||
.tune0_high = 0xffead0ff,
|
||||
.tune1 = 0x20091d9,
|
||||
.tune_high_min_millivolts = 864,
|
||||
}
|
||||
},
|
||||
{
|
||||
.speedo_id = 1,
|
||||
.process_id = 1,
|
||||
.min_millivolts = 837,
|
||||
.max_millivolts = 1227,
|
||||
CPU_CVB_TABLE,
|
||||
.cpu_dfll_data = {
|
||||
.tune0_low = 0xffead0ff,
|
||||
.tune0_high = 0xffead0ff,
|
||||
.tune1 = 0x25501d0,
|
||||
.tune_high_min_millivolts = 864,
|
||||
}
|
||||
},
|
||||
{
|
||||
.speedo_id = 0,
|
||||
.process_id = 0,
|
||||
.min_millivolts = 850,
|
||||
.max_millivolts = 1170,
|
||||
CPU_CVB_TABLE,
|
||||
.cpu_dfll_data = {
|
||||
.tune0_low = 0xffead0ff,
|
||||
.tune0_high = 0xffead0ff,
|
||||
.tune1 = 0x20091d9,
|
||||
.tune_high_min_millivolts = 864,
|
||||
}
|
||||
},
|
||||
{
|
||||
.speedo_id = 0,
|
||||
.process_id = 1,
|
||||
.min_millivolts = 850,
|
||||
.max_millivolts = 1170,
|
||||
CPU_CVB_TABLE,
|
||||
.cpu_dfll_data = {
|
||||
.tune0_low = 0xffead0ff,
|
||||
.tune0_high = 0xffead0ff,
|
||||
.tune1 = 0x25501d0,
|
||||
.tune_high_min_millivolts = 864,
|
||||
}
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dfll_fcpu_data tegra124_dfll_fcpu_data = {
|
||||
.cpu_max_freq_table = tegra124_cpu_max_freq_table,
|
||||
.cpu_max_freq_table_size = ARRAY_SIZE(tegra124_cpu_max_freq_table),
|
||||
.cpu_cvb_tables = tegra124_cpu_cvb_tables,
|
||||
.cpu_cvb_tables_size = ARRAY_SIZE(tegra124_cpu_cvb_tables)
|
||||
};
|
||||
|
||||
static const struct dfll_fcpu_data tegra210_dfll_fcpu_data = {
|
||||
.cpu_max_freq_table = tegra210_cpu_max_freq_table,
|
||||
.cpu_max_freq_table_size = ARRAY_SIZE(tegra210_cpu_max_freq_table),
|
||||
.cpu_cvb_tables = tegra210_cpu_cvb_tables,
|
||||
.cpu_cvb_tables_size = ARRAY_SIZE(tegra210_cpu_cvb_tables),
|
||||
};
|
||||
|
||||
static const struct of_device_id tegra124_dfll_fcpu_of_match[] = {
|
||||
{
|
||||
.compatible = "nvidia,tegra124-dfll",
|
||||
.data = &tegra124_dfll_fcpu_data,
|
||||
},
|
||||
{
|
||||
.compatible = "nvidia,tegra210-dfll",
|
||||
.data = &tegra210_dfll_fcpu_data
|
||||
},
|
||||
{ },
|
||||
};
|
||||
|
||||
static void get_alignment_from_dt(struct device *dev,
|
||||
struct rail_alignment *align)
|
||||
{
|
||||
if (of_property_read_u32(dev->of_node,
|
||||
"nvidia,pwm-voltage-step-microvolts",
|
||||
&align->step_uv))
|
||||
align->step_uv = 0;
|
||||
|
||||
if (of_property_read_u32(dev->of_node,
|
||||
"nvidia,pwm-min-microvolts",
|
||||
&align->offset_uv))
|
||||
align->offset_uv = 0;
|
||||
}
|
||||
|
||||
static int get_alignment_from_regulator(struct device *dev,
|
||||
struct rail_alignment *align)
|
||||
{
|
||||
struct regulator *reg = devm_regulator_get(dev, "vdd-cpu");
|
||||
|
||||
if (IS_ERR(reg))
|
||||
return PTR_ERR(reg);
|
||||
|
||||
align->offset_uv = regulator_list_voltage(reg, 0);
|
||||
align->step_uv = regulator_get_linear_step(reg);
|
||||
|
||||
devm_regulator_put(reg);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tegra124_dfll_fcpu_probe(struct platform_device *pdev)
|
||||
{
|
||||
int process_id, speedo_id, speedo_value, err;
|
||||
struct tegra_dfll_soc_data *soc;
|
||||
const struct dfll_fcpu_data *fcpu_data;
|
||||
struct rail_alignment align;
|
||||
|
||||
fcpu_data = of_device_get_match_data(&pdev->dev);
|
||||
if (!fcpu_data)
|
||||
return -ENODEV;
|
||||
|
||||
process_id = tegra_sku_info.cpu_process_id;
|
||||
speedo_id = tegra_sku_info.cpu_speedo_id;
|
||||
speedo_value = tegra_sku_info.cpu_speedo_value;
|
||||
|
||||
if (speedo_id >= ARRAY_SIZE(cpu_max_freq_table)) {
|
||||
if (speedo_id >= fcpu_data->cpu_max_freq_table_size) {
|
||||
dev_err(&pdev->dev, "unknown max CPU freq for speedo_id=%d\n",
|
||||
speedo_id);
|
||||
return -ENODEV;
|
||||
|
|
@ -107,12 +590,22 @@ static int tegra124_dfll_fcpu_probe(struct platform_device *pdev)
|
|||
return -ENODEV;
|
||||
}
|
||||
|
||||
soc->max_freq = cpu_max_freq_table[speedo_id];
|
||||
if (of_property_read_bool(pdev->dev.of_node, "nvidia,pwm-to-pmic")) {
|
||||
get_alignment_from_dt(&pdev->dev, &align);
|
||||
} else {
|
||||
err = get_alignment_from_regulator(&pdev->dev, &align);
|
||||
if (err)
|
||||
return err;
|
||||
}
|
||||
|
||||
soc->max_freq = fcpu_data->cpu_max_freq_table[speedo_id];
|
||||
|
||||
soc->cvb = tegra_cvb_add_opp_table(soc->dev, fcpu_data->cpu_cvb_tables,
|
||||
fcpu_data->cpu_cvb_tables_size,
|
||||
&align, process_id, speedo_id,
|
||||
speedo_value, soc->max_freq);
|
||||
soc->alignment = align;
|
||||
|
||||
soc->cvb = tegra_cvb_add_opp_table(soc->dev, tegra124_cpu_cvb_tables,
|
||||
ARRAY_SIZE(tegra124_cpu_cvb_tables),
|
||||
process_id, speedo_id, speedo_value,
|
||||
soc->max_freq);
|
||||
if (IS_ERR(soc->cvb)) {
|
||||
dev_err(&pdev->dev, "couldn't add OPP table: %ld\n",
|
||||
PTR_ERR(soc->cvb));
|
||||
|
|
@ -144,11 +637,6 @@ static int tegra124_dfll_fcpu_remove(struct platform_device *pdev)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id tegra124_dfll_fcpu_of_match[] = {
|
||||
{ .compatible = "nvidia,tegra124-dfll", },
|
||||
{ },
|
||||
};
|
||||
|
||||
static const struct dev_pm_ops tegra124_dfll_pm_ops = {
|
||||
SET_RUNTIME_PM_OPS(tegra_dfll_runtime_suspend,
|
||||
tegra_dfll_runtime_resume, NULL)
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* Utility functions for parsing Tegra CVB voltage tables
|
||||
*
|
||||
* Copyright (C) 2012-2014 NVIDIA Corporation. All rights reserved.
|
||||
* Copyright (C) 2012-2019 NVIDIA Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
|
|
@ -62,9 +62,9 @@ static int round_voltage(int mv, const struct rail_alignment *align, int up)
|
|||
}
|
||||
|
||||
static int build_opp_table(struct device *dev, const struct cvb_table *table,
|
||||
struct rail_alignment *align,
|
||||
int speedo_value, unsigned long max_freq)
|
||||
{
|
||||
const struct rail_alignment *align = &table->alignment;
|
||||
int i, ret, dfll_mv, min_mv, max_mv;
|
||||
|
||||
min_mv = round_voltage(table->min_millivolts, align, UP);
|
||||
|
|
@ -109,8 +109,9 @@ static int build_opp_table(struct device *dev, const struct cvb_table *table,
|
|||
*/
|
||||
const struct cvb_table *
|
||||
tegra_cvb_add_opp_table(struct device *dev, const struct cvb_table *tables,
|
||||
size_t count, int process_id, int speedo_id,
|
||||
int speedo_value, unsigned long max_freq)
|
||||
size_t count, struct rail_alignment *align,
|
||||
int process_id, int speedo_id, int speedo_value,
|
||||
unsigned long max_freq)
|
||||
{
|
||||
size_t i;
|
||||
int ret;
|
||||
|
|
@ -124,7 +125,8 @@ tegra_cvb_add_opp_table(struct device *dev, const struct cvb_table *tables,
|
|||
if (table->process_id != -1 && table->process_id != process_id)
|
||||
continue;
|
||||
|
||||
ret = build_opp_table(dev, table, speedo_value, max_freq);
|
||||
ret = build_opp_table(dev, table, align, speedo_value,
|
||||
max_freq);
|
||||
return ret ? ERR_PTR(ret) : table;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -41,6 +41,7 @@ struct cvb_cpu_dfll_data {
|
|||
u32 tune0_low;
|
||||
u32 tune0_high;
|
||||
u32 tune1;
|
||||
unsigned int tune_high_min_millivolts;
|
||||
};
|
||||
|
||||
struct cvb_table {
|
||||
|
|
@ -49,7 +50,6 @@ struct cvb_table {
|
|||
|
||||
int min_millivolts;
|
||||
int max_millivolts;
|
||||
struct rail_alignment alignment;
|
||||
|
||||
int speedo_scale;
|
||||
int voltage_scale;
|
||||
|
|
@ -59,8 +59,9 @@ struct cvb_table {
|
|||
|
||||
const struct cvb_table *
|
||||
tegra_cvb_add_opp_table(struct device *dev, const struct cvb_table *cvb_tables,
|
||||
size_t count, int process_id, int speedo_id,
|
||||
int speedo_value, unsigned long max_freq);
|
||||
size_t count, struct rail_alignment *align,
|
||||
int process_id, int speedo_id, int speedo_value,
|
||||
unsigned long max_freq);
|
||||
void tegra_cvb_remove_opp_table(struct device *dev,
|
||||
const struct cvb_table *table,
|
||||
unsigned long max_freq);
|
||||
|
|
|
|||
Loading…
Reference in New Issue