Merge remote-tracking branch 'asoc/fix/intel' into asoc-linus

This commit is contained in:
Mark Brown 2017-08-01 15:17:04 +01:00
commit 7e5fed09dd
3 changed files with 15 additions and 12 deletions

View File

@ -319,7 +319,9 @@ static int kabylake_rt5663_hw_params(struct snd_pcm_substream *substream,
int ret;
/* use ASRC for internal clocks, as PLL rate isn't multiple of BCLK */
rt5663_sel_asrc_clk_src(codec_dai->codec, RT5663_DA_STEREO_FILTER, 1);
rt5663_sel_asrc_clk_src(codec_dai->codec,
RT5663_DA_STEREO_FILTER | RT5663_AD_STEREO_FILTER,
RT5663_CLK_SEL_I2S1_ASRC);
ret = snd_soc_dai_set_sysclk(codec_dai,
RT5663_SCLK_S_MCLK, 24576000, SND_SOC_CLOCK_IN);
@ -349,19 +351,10 @@ static int kabylake_ssp0_hw_params(struct snd_pcm_substream *substream,
return ret;
}
ret = snd_soc_dai_set_pll(codec_dai, 0,
RT5514_PLL1_S_BCLK, RT5514_AIF1_BCLK_FREQ,
RT5514_AIF1_SYSCLK_FREQ);
if (ret < 0) {
dev_err(rtd->dev, "set bclk err: %d\n", ret);
return ret;
}
ret = snd_soc_dai_set_sysclk(codec_dai,
RT5514_SCLK_S_PLL1, RT5514_AIF1_SYSCLK_FREQ,
SND_SOC_CLOCK_IN);
RT5514_SCLK_S_MCLK, 24576000, SND_SOC_CLOCK_IN);
if (ret < 0) {
dev_err(rtd->dev, "set sclk err: %d\n", ret);
dev_err(rtd->dev, "set sysclk err: %d\n", ret);
return ret;
}
}

View File

@ -540,6 +540,14 @@ static void skl_setup_cpr_gateway_cfg(struct skl_sst *ctx,
cpr_mconfig->gtw_cfg.dma_buffer_size =
mconfig->dma_buffer_size * dma_io_buf;
/* fallback to 2ms default value */
if (!cpr_mconfig->gtw_cfg.dma_buffer_size) {
if (mconfig->hw_conn_type == SKL_CONN_SOURCE)
cpr_mconfig->gtw_cfg.dma_buffer_size = 2 * mconfig->obs;
else
cpr_mconfig->gtw_cfg.dma_buffer_size = 2 * mconfig->ibs;
}
cpr_mconfig->cpr_feature_mask = 0;
cpr_mconfig->gtw_cfg.config_length = 0;

View File

@ -941,6 +941,7 @@ static struct sst_acpi_mach sst_bxtp_devdata[] = {
.machine_quirk = sst_acpi_codec_list,
.quirk_data = &bxt_codecs,
},
{}
};
static struct sst_acpi_mach sst_kbl_devdata[] = {
@ -991,6 +992,7 @@ static struct sst_acpi_mach sst_glk_devdata[] = {
.drv_name = "glk_alc298s_i2s",
.fw_filename = "intel/dsp_fw_glk.bin",
},
{}
};
/* PCI IDs */