Add binding description for devices from
MT7623. Clock controller, iommu, JPEG Decoder and SMI conotroller. -----BEGIN PGP SIGNATURE----- iQJLBAABCAA1FiEEiUuSfQSYnG8EMsBltDliWyzx00MFAlu3HUQXHG1hdHRoaWFz LmJnZ0BnbWFpbC5jb20ACgkQtDliWyzx00Mp0hAAm8fb+uXd1a2Nh7pHTsZdoW1c Zvx+DPvFOywNnmXVvRBwVp1bsnKwqzCiezZL9TcOzvbdqlGXOhnW6AnpWawNmERc D5aCNC3xx7UN3DKSMI634U6y1aOZf2Z8mHLgTw24ZqR5ZHfGw18f2LLQZ3Q64pLq 6vNQbpF+dJYlBFFKw2lwq9yRCu6BaV56Z3uYblePrZru/pV38Tiw5UpxeOHeWaSA Jc2hGyNfA2LYOxr8eabLwRJtgMLaPxxzRH4quqRGlqEYBgi3NtfmEfLQUuqmXptC anb8BBD3RtWh9QBNjOEQA52qkCbJo6uB6FdyzPuHGpItwPKvNe/AYLxe3MxLc25u bjifnJN5LzjwD9+Psj13EIdhEC7+qBCqf8/dBiUcR3xI0YumhZ7dgBYd0JTR2I/7 vNJQSOXgSlsMCwhDLD8FCu/RgB38vMWdMocFD30nxc9BuuO+2qtKrpzEdO1sbkoh /gXcs92I18kXnig2dv6/NsWMoNv+nxK8wJDWuYcEPqFyrZl6xKcP/RV/QFLccBHK CDyjfIpW5DpIG3QEQYRsVWtOHOOOaCvl9qhSiVzOXU46+p4NBaNJu5H0IbTeTShe bRL0i+gZUP+LiaWQz8mRYoeBzM2BlrpJwxsgx3r91R9b4ciKwgoIJGkqBKNvAYHv EK6jSgTvmd9NBNNwl1w= =Tmq4 -----END PGP SIGNATURE----- Merge tag 'v4.19-next-dts32-2' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into next/dt Add binding description for devices from MT7623. Clock controller, iommu, JPEG Decoder and SMI conotroller. * tag 'v4.19-next-dts32-2' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux: dt-bindings: mediatek: Add bindig for MT7623 IOMMU and SMI dt-bindings: mediatek: Add JPEG Decoder binding for MT7623 dt-bindings: iommu: mediatek: Add binding for MT7623 dt-bindings: clock: mediatek: add support for MT7623 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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commit
7e6a361d17
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@ -10,6 +10,7 @@ Required Properties:
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- "mediatek,mt2712-apmixedsys", "syscon"
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- "mediatek,mt6797-apmixedsys"
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- "mediatek,mt7622-apmixedsys"
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- "mediatek,mt7623-apmixedsys", "mediatek,mt2701-apmixedsys"
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- "mediatek,mt8135-apmixedsys"
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- "mediatek,mt8173-apmixedsys"
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- #clock-cells: Must be 1
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@ -8,6 +8,7 @@ Required Properties:
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- compatible: Should be one of:
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- "mediatek,mt2701-audsys", "syscon"
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- "mediatek,mt7622-audsys", "syscon"
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- "mediatek,mt7623-audsys", "mediatek,mt2701-audsys", "syscon"
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- #clock-cells: Must be 1
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The AUDSYS controller uses the common clk binding from
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@ -8,6 +8,7 @@ Required Properties:
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- compatible: Should be:
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- "mediatek,mt2701-bdpsys", "syscon"
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- "mediatek,mt2712-bdpsys", "syscon"
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- "mediatek,mt7623-bdpsys", "mediatek,mt2701-bdpsys", "syscon"
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- #clock-cells: Must be 1
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The bdpsys controller uses the common clk binding from
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@ -8,6 +8,7 @@ Required Properties:
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- compatible: Should be:
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- "mediatek,mt2701-ethsys", "syscon"
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- "mediatek,mt7622-ethsys", "syscon"
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- "mediatek,mt7623-ethsys", "mediatek,mt2701-ethsys", "syscon"
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- #clock-cells: Must be 1
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- #reset-cells: Must be 1
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@ -9,6 +9,7 @@ Required Properties:
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- compatible: Should be:
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- "mediatek,mt2701-hifsys", "syscon"
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- "mediatek,mt7622-hifsys", "syscon"
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- "mediatek,mt7623-hifsys", "mediatek,mt2701-hifsys", "syscon"
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- #clock-cells: Must be 1
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The hifsys controller uses the common clk binding from
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@ -9,6 +9,7 @@ Required Properties:
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- "mediatek,mt2701-imgsys", "syscon"
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- "mediatek,mt2712-imgsys", "syscon"
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- "mediatek,mt6797-imgsys", "syscon"
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- "mediatek,mt7623-imgsys", "mediatek,mt2701-imgsys", "syscon"
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- "mediatek,mt8173-imgsys", "syscon"
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- #clock-cells: Must be 1
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@ -11,6 +11,7 @@ Required Properties:
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- "mediatek,mt2712-infracfg", "syscon"
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- "mediatek,mt6797-infracfg", "syscon"
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- "mediatek,mt7622-infracfg", "syscon"
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- "mediatek,mt7623-infracfg", "mediatek,mt2701-infracfg", "syscon"
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- "mediatek,mt8135-infracfg", "syscon"
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- "mediatek,mt8173-infracfg", "syscon"
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- #clock-cells: Must be 1
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@ -9,6 +9,7 @@ Required Properties:
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- "mediatek,mt2701-mmsys", "syscon"
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- "mediatek,mt2712-mmsys", "syscon"
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- "mediatek,mt6797-mmsys", "syscon"
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- "mediatek,mt7623-mmsys", "mediatek,mt2701-mmsys", "syscon"
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- "mediatek,mt8173-mmsys", "syscon"
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- #clock-cells: Must be 1
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@ -10,6 +10,7 @@ Required Properties:
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- "mediatek,mt2701-pericfg", "syscon"
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- "mediatek,mt2712-pericfg", "syscon"
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- "mediatek,mt7622-pericfg", "syscon"
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- "mediatek,mt7623-pericfg", "mediatek,mt2701-pericfg", "syscon"
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- "mediatek,mt8135-pericfg", "syscon"
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- "mediatek,mt8173-pericfg", "syscon"
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- #clock-cells: Must be 1
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@ -10,6 +10,7 @@ Required Properties:
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- "mediatek,mt2712-topckgen", "syscon"
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- "mediatek,mt6797-topckgen"
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- "mediatek,mt7622-topckgen"
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- "mediatek,mt7623-topckgen", "mediatek,mt2701-topckgen"
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- "mediatek,mt8135-topckgen"
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- "mediatek,mt8173-topckgen"
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- #clock-cells: Must be 1
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@ -9,6 +9,7 @@ Required Properties:
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- "mediatek,mt2701-vdecsys", "syscon"
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- "mediatek,mt2712-vdecsys", "syscon"
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- "mediatek,mt6797-vdecsys", "syscon"
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- "mediatek,mt7623-vdecsys", "mediatek,mt2701-vdecsys", "syscon"
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- "mediatek,mt8173-vdecsys", "syscon"
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- #clock-cells: Must be 1
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@ -41,6 +41,8 @@ Required properties:
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- compatible : must be one of the following string:
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"mediatek,mt2701-m4u" for mt2701 which uses generation one m4u HW.
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"mediatek,mt2712-m4u" for mt2712 which uses generation two m4u HW.
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"mediatek,mt7623-m4u", "mediatek,mt2701-m4u" for mt7623 which uses
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generation one m4u HW.
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"mediatek,mt8173-m4u" for mt8173 which uses generation two m4u HW.
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- reg : m4u register base and size.
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- interrupts : the interrupt of m4u.
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@ -51,7 +53,7 @@ Required properties:
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according to the local arbiter index, like larb0, larb1, larb2...
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- iommu-cells : must be 1. This is the mtk_m4u_id according to the HW.
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Specifies the mtk_m4u_id as defined in
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dt-binding/memory/mt2701-larb-port.h for mt2701,
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dt-binding/memory/mt2701-larb-port.h for mt2701, mt7623
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dt-binding/memory/mt2712-larb-port.h for mt2712, and
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dt-binding/memory/mt8173-larb-port.h for mt8173.
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@ -5,6 +5,7 @@ Mediatek JPEG Decoder is the JPEG decode hardware present in Mediatek SoCs
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Required properties:
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- compatible : must be one of the following string:
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"mediatek,mt8173-jpgdec"
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"mediatek,mt7623-jpgdec", "mediatek,mt2701-jpgdec"
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"mediatek,mt2701-jpgdec"
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- reg : physical base address of the jpeg decoder registers and length of
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memory mapped region.
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@ -17,6 +17,7 @@ Required properties:
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- compatible : must be one of :
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"mediatek,mt2701-smi-common"
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"mediatek,mt2712-smi-common"
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"mediatek,mt7623-smi-common", "mediatek,mt2701-smi-common"
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"mediatek,mt8173-smi-common"
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- reg : the register and size of the SMI block.
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- power-domains : a phandle to the power domain of this local arbiter.
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@ -6,6 +6,7 @@ Required properties:
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- compatible : must be one of :
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"mediatek,mt2701-smi-larb"
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"mediatek,mt2712-smi-larb"
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"mediatek,mt7623-smi-larb", "mediatek,mt2701-smi-larb"
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"mediatek,mt8173-smi-larb"
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- reg : the register and size of this local arbiter.
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- mediatek,smi : a phandle to the smi_common node.
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the register.
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- "smi" : It's the clock for transfer data and command.
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Required property for mt2701 and mt2712:
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Required property for mt2701, mt2712 and mt7623:
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- mediatek,larb-id :the hardware id of this larb.
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Example:
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