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clk: aspeed: Add RMII RCLK gates for both AST2500 MACs 

RCLK is a fixed 50MHz clock derived from HPLL that is described by a
single gate for each MAC.

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lkml.kernel.org/r/20191010020655.3776-3-andrew@aj.id.au
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Andrew Jeffery 2019-10-10 12:36:55 +10:30 committed by Stephen Boyd
parent 3696eebd81
commit 801b787a69
1 changed files with 26 additions and 1 deletions
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27
drivers/clk/clk-aspeed.c
View File

@ -14,7 +14,7 @@
#include "clk-aspeed.h"
#define ASPEED_NUM_CLKS 36
#define ASPEED_NUM_CLKS 38
#define ASPEED_RESET2_OFFSET 32
@ -28,6 +28,7 @@
#define AST2400_HPLL_BYPASS_EN BIT(17)
#define ASPEED_MISC_CTRL 0x2c
#define UART_DIV13_EN BIT(12)
#define ASPEED_MAC_CLK_DLY 0x48
#define ASPEED_STRAP 0x70
#define CLKIN_25MHZ_EN BIT(23)
#define AST2400_CLK_SOURCE_SEL BIT(18)
@ -462,6 +463,30 @@ static int aspeed_clk_probe(struct platform_device *pdev)
return PTR_ERR(hw);
aspeed_clk_data->hws[ASPEED_CLK_MAC] = hw;
if (of_device_is_compatible(pdev->dev.of_node, "aspeed,ast2500-scu")) {
/* RMII 50MHz RCLK */
hw = clk_hw_register_fixed_rate(dev, "mac12rclk", "hpll", 0,
50000000);
if (IS_ERR(hw))
return PTR_ERR(hw);
/* RMII1 50MHz (RCLK) output enable */
hw = clk_hw_register_gate(dev, "mac1rclk", "mac12rclk", 0,
scu_base + ASPEED_MAC_CLK_DLY, 29, 0,
&aspeed_clk_lock);
if (IS_ERR(hw))
return PTR_ERR(hw);
aspeed_clk_data->hws[ASPEED_CLK_MAC1RCLK] = hw;
/* RMII2 50MHz (RCLK) output enable */
hw = clk_hw_register_gate(dev, "mac2rclk", "mac12rclk", 0,
scu_base + ASPEED_MAC_CLK_DLY, 30, 0,
&aspeed_clk_lock);
if (IS_ERR(hw))
return PTR_ERR(hw);
aspeed_clk_data->hws[ASPEED_CLK_MAC2RCLK] = hw;
}
/* LPC Host (LHCLK) clock divider */
hw = clk_hw_register_divider_table(dev, "lhclk", "hpll", 0,
scu_base + ASPEED_CLK_SELECTION, 20, 3, 0,