dmaengine: sun6i: Add a quirk for setting mode fields
H6 DMA has mode fields in different position than any other currently supported DMA controller. Add a quirk for that. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Clément Péron <peron.clem@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Jernej Skrabec
Vinod Koul
parent
67f3405511
commit
802440bdf3
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@ -70,15 +70,13 @@
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#define DMA_CHAN_CUR_CFG 0x0c
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#define DMA_CHAN_MAX_DRQ_A31 0x1f
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#define DMA_CHAN_CFG_SRC_DRQ_A31(x) ((x) & DMA_CHAN_MAX_DRQ_A31)
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#define DMA_CHAN_CFG_SRC_IO_MODE BIT(5)
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#define DMA_CHAN_CFG_SRC_LINEAR_MODE (0 << 5)
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#define DMA_CHAN_CFG_SRC_MODE_A31(x) (((x) & 0x1) << 5)
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#define DMA_CHAN_CFG_SRC_BURST_A31(x) (((x) & 0x3) << 7)
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#define DMA_CHAN_CFG_SRC_BURST_H3(x) (((x) & 0x3) << 6)
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#define DMA_CHAN_CFG_SRC_WIDTH(x) (((x) & 0x3) << 9)
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#define DMA_CHAN_CFG_DST_DRQ_A31(x) (DMA_CHAN_CFG_SRC_DRQ_A31(x) << 16)
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#define DMA_CHAN_CFG_DST_IO_MODE (DMA_CHAN_CFG_SRC_IO_MODE << 16)
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#define DMA_CHAN_CFG_DST_LINEAR_MODE (DMA_CHAN_CFG_SRC_LINEAR_MODE << 16)
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#define DMA_CHAN_CFG_DST_MODE_A31(x) (DMA_CHAN_CFG_SRC_MODE_A31(x) << 16)
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#define DMA_CHAN_CFG_DST_BURST_A31(x) (DMA_CHAN_CFG_SRC_BURST_A31(x) << 16)
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#define DMA_CHAN_CFG_DST_BURST_H3(x) (DMA_CHAN_CFG_SRC_BURST_H3(x) << 16)
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#define DMA_CHAN_CFG_DST_WIDTH(x) (DMA_CHAN_CFG_SRC_WIDTH(x) << 16)
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@ -98,6 +96,8 @@
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#define LLI_LAST_ITEM 0xfffff800
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#define NORMAL_WAIT 8
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#define DRQ_SDRAM 1
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#define LINEAR_MODE 0
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#define IO_MODE 1
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/* forward declaration */
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struct sun6i_dma_dev;
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@ -126,6 +126,7 @@ struct sun6i_dma_config {
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void (*clock_autogate_enable)(struct sun6i_dma_dev *);
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void (*set_burst_length)(u32 *p_cfg, s8 src_burst, s8 dst_burst);
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void (*set_drq)(u32 *p_cfg, s8 src_drq, s8 dst_drq);
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void (*set_mode)(u32 *p_cfg, s8 src_mode, s8 dst_mode);
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u32 src_burst_lengths;
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u32 dst_burst_lengths;
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u32 src_addr_widths;
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@ -318,6 +319,12 @@ static void sun6i_set_drq_a31(u32 *p_cfg, s8 src_drq, s8 dst_drq)
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DMA_CHAN_CFG_DST_DRQ_A31(dst_drq);
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}
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static void sun6i_set_mode_a31(u32 *p_cfg, s8 src_mode, s8 dst_mode)
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{
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*p_cfg |= DMA_CHAN_CFG_SRC_MODE_A31(src_mode) |
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DMA_CHAN_CFG_DST_MODE_A31(dst_mode);
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}
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static size_t sun6i_get_chan_size(struct sun6i_pchan *pchan)
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{
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struct sun6i_desc *txd = pchan->desc;
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@ -641,13 +648,12 @@ static struct dma_async_tx_descriptor *sun6i_dma_prep_dma_memcpy(
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burst = convert_burst(8);
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width = convert_buswidth(DMA_SLAVE_BUSWIDTH_4_BYTES);
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v_lli->cfg = DMA_CHAN_CFG_DST_LINEAR_MODE |
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DMA_CHAN_CFG_SRC_LINEAR_MODE |
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DMA_CHAN_CFG_SRC_WIDTH(width) |
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v_lli->cfg = DMA_CHAN_CFG_SRC_WIDTH(width) |
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DMA_CHAN_CFG_DST_WIDTH(width);
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sdev->cfg->set_burst_length(&v_lli->cfg, burst, burst);
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sdev->cfg->set_drq(&v_lli->cfg, DRQ_SDRAM, DRQ_SDRAM);
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sdev->cfg->set_mode(&v_lli->cfg, LINEAR_MODE, LINEAR_MODE);
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sun6i_dma_lli_add(NULL, v_lli, p_lli, txd);
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@ -699,10 +705,9 @@ static struct dma_async_tx_descriptor *sun6i_dma_prep_slave_sg(
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if (dir == DMA_MEM_TO_DEV) {
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v_lli->src = sg_dma_address(sg);
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v_lli->dst = sconfig->dst_addr;
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v_lli->cfg = lli_cfg |
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DMA_CHAN_CFG_DST_IO_MODE |
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DMA_CHAN_CFG_SRC_LINEAR_MODE;
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v_lli->cfg = lli_cfg;
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sdev->cfg->set_drq(&v_lli->cfg, DRQ_SDRAM, vchan->port);
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sdev->cfg->set_mode(&v_lli->cfg, LINEAR_MODE, IO_MODE);
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dev_dbg(chan2dev(chan),
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"%s; chan: %d, dest: %pad, src: %pad, len: %u. flags: 0x%08lx\n",
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@ -713,10 +718,9 @@ static struct dma_async_tx_descriptor *sun6i_dma_prep_slave_sg(
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} else {
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v_lli->src = sconfig->src_addr;
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v_lli->dst = sg_dma_address(sg);
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v_lli->cfg = lli_cfg |
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DMA_CHAN_CFG_DST_LINEAR_MODE |
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DMA_CHAN_CFG_SRC_IO_MODE;
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v_lli->cfg = lli_cfg;
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sdev->cfg->set_drq(&v_lli->cfg, vchan->port, DRQ_SDRAM);
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sdev->cfg->set_mode(&v_lli->cfg, IO_MODE, LINEAR_MODE);
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dev_dbg(chan2dev(chan),
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"%s; chan: %d, dest: %pad, src: %pad, len: %u. flags: 0x%08lx\n",
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@ -782,17 +786,15 @@ static struct dma_async_tx_descriptor *sun6i_dma_prep_dma_cyclic(
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if (dir == DMA_MEM_TO_DEV) {
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v_lli->src = buf_addr + period_len * i;
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v_lli->dst = sconfig->dst_addr;
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v_lli->cfg = lli_cfg |
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DMA_CHAN_CFG_DST_IO_MODE |
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DMA_CHAN_CFG_SRC_LINEAR_MODE;
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v_lli->cfg = lli_cfg;
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sdev->cfg->set_drq(&v_lli->cfg, DRQ_SDRAM, vchan->port);
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sdev->cfg->set_mode(&v_lli->cfg, LINEAR_MODE, IO_MODE);
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} else {
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v_lli->src = sconfig->src_addr;
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v_lli->dst = buf_addr + period_len * i;
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v_lli->cfg = lli_cfg |
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DMA_CHAN_CFG_DST_LINEAR_MODE |
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DMA_CHAN_CFG_SRC_IO_MODE;
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v_lli->cfg = lli_cfg;
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sdev->cfg->set_drq(&v_lli->cfg, vchan->port, DRQ_SDRAM);
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sdev->cfg->set_mode(&v_lli->cfg, IO_MODE, LINEAR_MODE);
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}
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prev = sun6i_dma_lli_add(prev, v_lli, p_lli, txd);
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@ -1058,6 +1060,7 @@ static struct sun6i_dma_config sun6i_a31_dma_cfg = {
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.nr_max_vchans = 53,
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.set_burst_length = sun6i_set_burst_length_a31,
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.set_drq = sun6i_set_drq_a31,
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.set_mode = sun6i_set_mode_a31,
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.src_burst_lengths = BIT(1) | BIT(8),
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.dst_burst_lengths = BIT(1) | BIT(8),
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.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
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@ -1080,6 +1083,7 @@ static struct sun6i_dma_config sun8i_a23_dma_cfg = {
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.clock_autogate_enable = sun6i_enable_clock_autogate_a23,
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.set_burst_length = sun6i_set_burst_length_a31,
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.set_drq = sun6i_set_drq_a31,
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.set_mode = sun6i_set_mode_a31,
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.src_burst_lengths = BIT(1) | BIT(8),
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.dst_burst_lengths = BIT(1) | BIT(8),
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.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
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@ -1097,6 +1101,7 @@ static struct sun6i_dma_config sun8i_a83t_dma_cfg = {
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.clock_autogate_enable = sun6i_enable_clock_autogate_a23,
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.set_burst_length = sun6i_set_burst_length_a31,
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.set_drq = sun6i_set_drq_a31,
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.set_mode = sun6i_set_mode_a31,
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.src_burst_lengths = BIT(1) | BIT(8),
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.dst_burst_lengths = BIT(1) | BIT(8),
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.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
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@ -1121,6 +1126,7 @@ static struct sun6i_dma_config sun8i_h3_dma_cfg = {
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.clock_autogate_enable = sun6i_enable_clock_autogate_h3,
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.set_burst_length = sun6i_set_burst_length_h3,
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.set_drq = sun6i_set_drq_a31,
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.set_mode = sun6i_set_mode_a31,
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.src_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16),
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.dst_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16),
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.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
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@ -1141,6 +1147,7 @@ static struct sun6i_dma_config sun50i_a64_dma_cfg = {
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.clock_autogate_enable = sun6i_enable_clock_autogate_h3,
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.set_burst_length = sun6i_set_burst_length_h3,
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.set_drq = sun6i_set_drq_a31,
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.set_mode = sun6i_set_mode_a31,
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.src_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16),
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.dst_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16),
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.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
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@ -1165,6 +1172,7 @@ static struct sun6i_dma_config sun8i_v3s_dma_cfg = {
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.clock_autogate_enable = sun6i_enable_clock_autogate_a23,
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.set_burst_length = sun6i_set_burst_length_a31,
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.set_drq = sun6i_set_drq_a31,
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.set_mode = sun6i_set_mode_a31,
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.src_burst_lengths = BIT(1) | BIT(8),
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.dst_burst_lengths = BIT(1) | BIT(8),
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.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
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