ARM: cns3xxx: Convert PCI to use generic config accessors
Convert the cns3xxx PCI driver to use the generic config access functions. This changes accesses from __raw_readl/__raw_writel to readl/writel. [arnd: remove extra open parenthesis] Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Krzysztof Hałasa <khalasa@piap.pl> CC: Russell King <linux@arm.linux.org.uk> CC: linux-arm-kernel@lists.infradead.org
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@ -54,7 +54,7 @@ static struct cns3xxx_pcie *pbus_to_cnspci(struct pci_bus *bus)
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return sysdata_to_cnspci(bus->sysdata);
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return sysdata_to_cnspci(bus->sysdata);
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}
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}
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static void __iomem *cns3xxx_pci_cfg_base(struct pci_bus *bus,
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static void __iomem *cns3xxx_pci_map_bus(struct pci_bus *bus,
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unsigned int devfn, int where)
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unsigned int devfn, int where)
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{
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{
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struct cns3xxx_pcie *cnspci = pbus_to_cnspci(bus);
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struct cns3xxx_pcie *cnspci = pbus_to_cnspci(bus);
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@ -91,55 +91,22 @@ static void __iomem *cns3xxx_pci_cfg_base(struct pci_bus *bus,
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static int cns3xxx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
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static int cns3xxx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 *val)
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int where, int size, u32 *val)
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{
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{
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u32 v;
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int ret;
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void __iomem *base;
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u32 mask = (0x1ull << (size * 8)) - 1;
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u32 mask = (0x1ull << (size * 8)) - 1;
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int shift = (where % 4) * 8;
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int shift = (where % 4) * 8;
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base = cns3xxx_pci_cfg_base(bus, devfn, where);
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ret = pci_generic_config_read32(bus, devfn, where, size, val);
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if (!base) {
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*val = 0xffffffff;
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return PCIBIOS_SUCCESSFUL;
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}
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v = __raw_readl(base);
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if (ret == PCIBIOS_SUCCESSFUL && !bus->number && !devfn &&
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(where & 0xffc) == PCI_CLASS_REVISION)
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if (bus->number == 0 && devfn == 0 &&
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(where & 0xffc) == PCI_CLASS_REVISION) {
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/*
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/*
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* RC's class is 0xb, but Linux PCI driver needs 0x604
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* RC's class is 0xb, but Linux PCI driver needs 0x604
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* for a PCIe bridge. So we must fixup the class code
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* for a PCIe bridge. So we must fixup the class code
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* to 0x604 here.
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* to 0x604 here.
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*/
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*/
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v &= 0xff;
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*val = ((((*val << shift) & 0xff) | (0x604 << 16)) >> shift) & mask;
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v |= 0x604 << 16;
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}
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*val = (v >> shift) & mask;
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return ret;
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return PCIBIOS_SUCCESSFUL;
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}
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static int cns3xxx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 val)
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{
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u32 v;
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void __iomem *base;
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u32 mask = (0x1ull << (size * 8)) - 1;
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int shift = (where % 4) * 8;
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base = cns3xxx_pci_cfg_base(bus, devfn, where);
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if (!base)
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return PCIBIOS_SUCCESSFUL;
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v = __raw_readl(base);
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v &= ~(mask << shift);
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v |= (val & mask) << shift;
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__raw_writel(v, base);
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return PCIBIOS_SUCCESSFUL;
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}
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}
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static int cns3xxx_pci_setup(int nr, struct pci_sys_data *sys)
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static int cns3xxx_pci_setup(int nr, struct pci_sys_data *sys)
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@ -158,8 +125,9 @@ static int cns3xxx_pci_setup(int nr, struct pci_sys_data *sys)
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}
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}
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static struct pci_ops cns3xxx_pcie_ops = {
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static struct pci_ops cns3xxx_pcie_ops = {
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.map_bus = cns3xxx_pci_map_bus,
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.read = cns3xxx_pci_read_config,
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.read = cns3xxx_pci_read_config,
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.write = cns3xxx_pci_write_config,
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.write = pci_generic_config_write,
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};
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};
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static int cns3xxx_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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static int cns3xxx_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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