arm: Xilinx Zynq dt patches for v3.15
- Define fclk-enable property -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.10 (GNU/Linux) iEYEABECAAYFAlMGGzAACgkQykllyylKDCGQ8QCePYiY0VQN7yn7z2WZ2preAClx KDUAnilZJyUjsJpuXXusByxPDTOaJlYJ =5NA7 -----END PGP SIGNATURE----- Merge tag 'zynq-dt-for-3.15' of git://git.xilinx.com/linux-xlnx into next/dt Merge "arm: Xilinx Zynq dt patches for v3.15" from Michal Simek: - Define fclk-enable property * tag 'zynq-dt-for-3.15' of git://git.xilinx.com/linux-xlnx: arm: dt: zynq: Add fclk-enable property to clkc node Signed-off-by: Olof Johansson <olof@lixom.net>
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813004a3f1
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@ -134,6 +134,7 @@ clkc: clkc {
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#clock-cells = <1>;
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#clock-cells = <1>;
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compatible = "xlnx,ps7-clkc";
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compatible = "xlnx,ps7-clkc";
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ps-clk-frequency = <33333333>;
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ps-clk-frequency = <33333333>;
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fclk-enable = <0>;
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clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
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clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
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"cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
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"cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
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"dci", "lqspi", "smc", "pcap", "gem0", "gem1",
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"dci", "lqspi", "smc", "pcap", "gem0", "gem1",
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