drm/nouveau/fb/ramnv50: GDDR3 script for NVA0
This looks surprisingly similar to scripts on earlier cards as well but they don't seem to work just yet. That... and I don't have any, which makes it a tough job to reverse engineer. Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Roy Spliet
Ben Skeggs
parent
c25bf7b615
commit
82a74fd293
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@ -39,10 +39,19 @@ struct nv50_ramseq {
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struct hwsq_reg r_0x004008;
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struct hwsq_reg r_0x00400c;
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struct hwsq_reg r_0x00c040;
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struct hwsq_reg r_0x100200;
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struct hwsq_reg r_0x100210;
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struct hwsq_reg r_0x10021c;
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struct hwsq_reg r_0x1002d0;
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struct hwsq_reg r_0x1002d4;
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struct hwsq_reg r_0x1002dc;
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struct hwsq_reg r_0x10053c;
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struct hwsq_reg r_0x1005a0;
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struct hwsq_reg r_0x1005a4;
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struct hwsq_reg r_0x100710;
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struct hwsq_reg r_0x100714;
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struct hwsq_reg r_0x100718;
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struct hwsq_reg r_0x10071c;
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struct hwsq_reg r_0x100da0;
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struct hwsq_reg r_0x100e20;
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struct hwsq_reg r_0x100e24;
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@ -135,7 +144,13 @@ nv50_ram_timing_calc(struct nvkm_fb *pfb, u32 *timing)
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}
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#undef T
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#define QFX5800NVA0 1
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static void
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nvkm_sddr2_dll_reset(struct nv50_ramseq *hwsq)
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{
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ram_mask(hwsq, mr[0], 0x100, 0x100);
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ram_mask(hwsq, mr[0], 0x100, 0x000);
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ram_nsec(hwsq, 24000);
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}
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static int
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nv50_ram_calc(struct nvkm_fb *pfb, u32 freq)
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@ -148,7 +163,7 @@ nv50_ram_calc(struct nvkm_fb *pfb, u32 freq)
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struct nvkm_ram_data *next;
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u8 ver, hdr, cnt, len, strap, size;
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u32 data;
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u32 r100da0;
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u32 r100da0, r004008, unk710, unk714, unk718, unk71c;
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int N1, M1, N2, M2, P;
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int ret, i;
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u32 timing[9];
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@ -220,12 +235,8 @@ nv50_ram_calc(struct nvkm_fb *pfb, u32 freq)
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if (ret)
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return ret;
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/* XXX: 750MHz seems rather arbitrary */
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if (freq <= 750000) {
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r100da0 = 0x00000010;
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} else {
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r100da0 = 0x00000000;
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}
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/* Always disable this bit during reclock */
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ram_mask(hwsq, 0x100200, 0x00000800, 0x00000000);
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ram_wait(hwsq, 0x01, 0x00); /* wait for !vblank */
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ram_wait(hwsq, 0x01, 0x01); /* wait for vblank */
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@ -234,6 +245,7 @@ nv50_ram_calc(struct nvkm_fb *pfb, u32 freq)
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ram_nsec(hwsq, 8000);
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ram_setf(hwsq, 0x10, 0x00); /* disable fb */
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ram_wait(hwsq, 0x00, 0x01); /* wait for fb disabled */
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ram_nsec(hwsq, 2000);
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ram_wr32(hwsq, 0x1002d4, 0x00000001); /* precharge */
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ram_wr32(hwsq, 0x1002d0, 0x00000001); /* refresh */
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@ -253,18 +265,33 @@ nv50_ram_calc(struct nvkm_fb *pfb, u32 freq)
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if (ret < 0)
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return ret;
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ram_mask(hwsq, 0x00c040, 0xc000c000, 0x0000c000);
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ram_mask(hwsq, 0x004008, 0x00000200, 0x00000200);
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ram_mask(hwsq, 0x00400c, 0x0000ffff, (N1 << 8) | M1);
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ram_mask(hwsq, 0x004008, 0x81ff0000, 0x80000000 | (mpll.bias_p << 19) |
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(P << 22) | (P << 16));
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/* XXX: 750MHz seems rather arbitrary */
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if (freq <= 750000) {
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r100da0 = 0x00000010;
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r004008 = 0x90000000;
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} else {
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r100da0 = 0x00000000;
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r004008 = 0x80000000;
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}
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r004008 |= (mpll.bias_p << 19) | (P << 22) | (P << 16);
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ram_mask(hwsq, 0x00c040, 0xc000c000, 0x0000c000);
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/* XXX: Is rammap_00_16_40 the DLL bit we've seen in GT215? Why does
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* it have a different rammap bit from DLLoff? */
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ram_mask(hwsq, 0x004008, 0x00004200, 0x00000200 |
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next->bios.rammap_00_16_40 << 14);
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ram_mask(hwsq, 0x00400c, 0x0000ffff, (N1 << 8) | M1);
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ram_mask(hwsq, 0x004008, 0x91ff0000, r004008);
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if (nv_device(pfb)->chipset >= 0x96)
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ram_wr32(hwsq, 0x100da0, r100da0);
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ram_nsec(hwsq, 64000); /*XXX*/
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ram_nsec(hwsq, 32000); /*XXX*/
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if (nv_device(pfb)->chipset == 0xa0)
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ram_wr32(hwsq, 0x100da0, r100da0); /*XXX: here?*/
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ram_nsec(hwsq, 96000); /*XXX*/
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ram_mask(hwsq, 0x004008, 0x00002200, 0x00002000);
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ram_wr32(hwsq, 0x1002dc, 0x00000000); /* disable self-refresh */
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ram_wr32(hwsq, 0x1002d4, 0x00000001); /* disable self-refresh */
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ram_wr32(hwsq, 0x100210, 0x80000000); /* enable auto-refresh */
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ram_nsec(hwsq, 12000);
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@ -275,9 +302,10 @@ nv50_ram_calc(struct nvkm_fb *pfb, u32 freq)
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ram_mask(hwsq, mr[0], 0x000, 0x000);
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break;
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case NV_MEM_TYPE_GDDR3:
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ram_mask(hwsq, mr[2], 0x000, 0x000);
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ram_nuke(hwsq, mr[1]); /* force update */
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ram_wr32(hwsq, mr[1], ram->base.mr[1]);
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ram_nuke(hwsq, mr[0]); /* force update */
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ram_mask(hwsq, mr[0], 0x000, 0x000);
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ram_wr32(hwsq, mr[0], ram->base.mr[0]);
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break;
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default:
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break;
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@ -293,20 +321,62 @@ nv50_ram_calc(struct nvkm_fb *pfb, u32 freq)
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ram_mask(hwsq, timing[4], 0xffffffff, timing[4]);
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ram_mask(hwsq, timing[5], 0xffffffff, timing[5]);
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#if QFX5800NVA0
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ram_nuke(hwsq, 0x100e24);
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ram_mask(hwsq, 0x100e24, 0x00000000, 0x00000000);
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ram_nuke(hwsq, 0x100e20);
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ram_mask(hwsq, 0x100e20, 0x00000000, 0x00000000);
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#endif
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if (!next->bios.ramcfg_00_03_02)
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ram_mask(hwsq, 0x10021c, 0x00010000, 0x00000000);
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ram_mask(hwsq, 0x100200, 0x00001000, !next->bios.ramcfg_00_04_02 << 12);
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ram_mask(hwsq, mr[0], 0x100, 0x100);
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ram_mask(hwsq, mr[0], 0x100, 0x000);
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/* XXX: A lot of this could be "chipset"/"ram type" specific stuff */
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unk710 = ram_rd32(hwsq, 0x100710) & ~0x00000101;
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unk714 = ram_rd32(hwsq, 0x100714) & ~0xf0000020;
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unk718 = ram_rd32(hwsq, 0x100718) & ~0x00000100;
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unk71c = ram_rd32(hwsq, 0x10071c) & ~0x00000100;
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if ( next->bios.ramcfg_00_03_01)
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unk71c |= 0x00000100;
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if ( next->bios.ramcfg_00_03_02)
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unk710 |= 0x00000100;
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if (!next->bios.ramcfg_00_03_08) {
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unk710 |= 0x1;
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unk714 |= 0x20;
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}
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if ( next->bios.ramcfg_00_04_04)
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unk714 |= 0x70000000;
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if ( next->bios.ramcfg_00_04_20)
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unk718 |= 0x00000100;
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ram_mask(hwsq, 0x100714, 0xffffffff, unk714);
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ram_mask(hwsq, 0x10071c, 0xffffffff, unk71c);
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ram_mask(hwsq, 0x100718, 0xffffffff, unk718);
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ram_mask(hwsq, 0x100710, 0xffffffff, unk710);
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if (next->bios.rammap_00_16_20) {
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ram_wr32(hwsq, 0x1005a0, next->bios.ramcfg_00_07 << 16 |
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next->bios.ramcfg_00_06 << 8 |
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next->bios.ramcfg_00_05);
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ram_wr32(hwsq, 0x1005a4, next->bios.ramcfg_00_09 << 8 |
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next->bios.ramcfg_00_08);
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ram_mask(hwsq, 0x10053c, 0x00001000, 0x00000000);
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} else {
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ram_mask(hwsq, 0x10053c, 0x00001000, 0x00001000);
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}
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ram_mask(hwsq, mr[1], 0xffffffff, ram->base.mr[1]);
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/* Reset DLL */
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if (!next->bios.ramcfg_DLLoff)
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nvkm_sddr2_dll_reset(hwsq);
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ram_setf(hwsq, 0x10, 0x01); /* enable fb */
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ram_wait(hwsq, 0x00, 0x00); /* wait for fb enabled */
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ram_wr32(hwsq, 0x611200, 0x00003330);
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ram_wr32(hwsq, 0x002504, 0x00000000); /* un-block fifo */
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if (next->bios.rammap_00_17_02)
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ram_mask(hwsq, 0x100200, 0x00000800, 0x00000800);
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if (!next->bios.rammap_00_16_40)
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ram_mask(hwsq, 0x004008, 0x00004000, 0x00000000);
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if (next->bios.ramcfg_00_03_02)
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ram_mask(hwsq, 0x10021c, 0x00010000, 0x00010000);
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return 0;
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}
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@ -522,12 +592,12 @@ nv50_ram_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
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return ret;
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switch (ram->base.type) {
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case NV_MEM_TYPE_DDR2:
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case NV_MEM_TYPE_GDDR3:
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ram->base.calc = nv50_ram_calc;
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ram->base.prog = nv50_ram_prog;
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ram->base.tidy = nv50_ram_tidy;
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break;
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case NV_MEM_TYPE_DDR2:
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default:
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nv_warn(ram, "reclocking of this ram type unsupported\n");
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return 0;
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@ -537,10 +607,19 @@ nv50_ram_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
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ram->hwsq.r_0x00c040 = hwsq_reg(0x00c040);
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ram->hwsq.r_0x004008 = hwsq_reg(0x004008);
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ram->hwsq.r_0x00400c = hwsq_reg(0x00400c);
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ram->hwsq.r_0x100200 = hwsq_reg(0x100200);
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ram->hwsq.r_0x100210 = hwsq_reg(0x100210);
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ram->hwsq.r_0x10021c = hwsq_reg(0x10021c);
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ram->hwsq.r_0x1002d0 = hwsq_reg(0x1002d0);
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ram->hwsq.r_0x1002d4 = hwsq_reg(0x1002d4);
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ram->hwsq.r_0x1002dc = hwsq_reg(0x1002dc);
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ram->hwsq.r_0x10053c = hwsq_reg(0x10053c);
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ram->hwsq.r_0x1005a0 = hwsq_reg(0x1005a0);
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ram->hwsq.r_0x1005a4 = hwsq_reg(0x1005a4);
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ram->hwsq.r_0x100710 = hwsq_reg(0x100710);
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ram->hwsq.r_0x100714 = hwsq_reg(0x100714);
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ram->hwsq.r_0x100718 = hwsq_reg(0x100718);
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ram->hwsq.r_0x10071c = hwsq_reg(0x10071c);
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ram->hwsq.r_0x100da0 = hwsq_stride(0x100da0, 4, ram->base.part_mask);
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ram->hwsq.r_0x100e20 = hwsq_reg(0x100e20);
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ram->hwsq.r_0x100e24 = hwsq_reg(0x100e24);
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