crypto: hisilicon - Add debugfs for HPRE
HiSilicon HPRE engine driver uses debugfs to provide debug information, the usage can be found in /Documentation/ABI/testing/debugfs-hisi-hpre. Signed-off-by: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Hui Tang <tanghui20@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
parent
b492f82fce
commit
8489741516
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@ -9,11 +9,45 @@
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#define HPRE_SQE_SIZE sizeof(struct hpre_sqe)
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#define HPRE_PF_DEF_Q_NUM 64
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#define HPRE_PF_DEF_Q_BASE 0
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#define HPRE_CLUSTERS_NUM 4
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enum {
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HPRE_CLUSTER0,
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HPRE_CLUSTER1,
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HPRE_CLUSTER2,
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HPRE_CLUSTER3,
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HPRE_CLUSTERS_NUM,
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};
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enum hpre_ctrl_dbgfs_file {
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HPRE_CURRENT_QM,
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HPRE_CLEAR_ENABLE,
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HPRE_CLUSTER_CTRL,
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HPRE_DEBUG_FILE_NUM,
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};
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#define HPRE_DEBUGFS_FILE_NUM (HPRE_DEBUG_FILE_NUM + HPRE_CLUSTERS_NUM - 1)
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struct hpre_debugfs_file {
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int index;
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enum hpre_ctrl_dbgfs_file type;
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spinlock_t lock;
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struct hpre_debug *debug;
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};
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/*
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* One HPRE controller has one PF and multiple VFs, some global configurations
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* which PF has need this structure.
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* Just relevant for PF.
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*/
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struct hpre_debug {
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struct dentry *debug_root;
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struct hpre_debugfs_file files[HPRE_DEBUGFS_FILE_NUM];
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};
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struct hpre {
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struct hisi_qm qm;
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struct list_head list;
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struct hpre_debug debug;
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u32 num_vfs;
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unsigned long status;
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};
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@ -3,6 +3,7 @@
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#include <linux/acpi.h>
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#include <linux/aer.h>
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#include <linux/bitops.h>
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#include <linux/debugfs.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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@ -84,6 +85,7 @@
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static LIST_HEAD(hpre_list);
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static DEFINE_MUTEX(hpre_list_lock);
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static const char hpre_name[] = "hisi_hpre";
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static struct dentry *hpre_debugfs_root;
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static const struct pci_device_id hpre_dev_ids[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HPRE_PCI_DEVICE_ID) },
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{ PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HPRE_PCI_VF_DEVICE_ID) },
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@ -97,6 +99,12 @@ struct hpre_hw_error {
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const char *msg;
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};
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static const char * const hpre_debug_file_name[] = {
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[HPRE_CURRENT_QM] = "current_qm",
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[HPRE_CLEAR_ENABLE] = "rdclr_en",
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[HPRE_CLUSTER_CTRL] = "cluster_ctrl",
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};
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static const struct hpre_hw_error hpre_hw_errors[] = {
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{ .int_msk = BIT(0), .msg = "hpre_ecc_1bitt_err" },
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{ .int_msk = BIT(1), .msg = "hpre_ecc_2bit_err" },
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@ -113,6 +121,42 @@ static const struct hpre_hw_error hpre_hw_errors[] = {
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{ /* sentinel */ }
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};
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static const u64 hpre_cluster_offsets[] = {
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[HPRE_CLUSTER0] =
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HPRE_CLSTR_BASE + HPRE_CLUSTER0 * HPRE_CLSTR_ADDR_INTRVL,
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[HPRE_CLUSTER1] =
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HPRE_CLSTR_BASE + HPRE_CLUSTER1 * HPRE_CLSTR_ADDR_INTRVL,
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[HPRE_CLUSTER2] =
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HPRE_CLSTR_BASE + HPRE_CLUSTER2 * HPRE_CLSTR_ADDR_INTRVL,
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[HPRE_CLUSTER3] =
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HPRE_CLSTR_BASE + HPRE_CLUSTER3 * HPRE_CLSTR_ADDR_INTRVL,
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};
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static struct debugfs_reg32 hpre_cluster_dfx_regs[] = {
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{"CORES_EN_STATUS ", HPRE_CORE_EN_OFFSET},
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{"CORES_INI_CFG ", HPRE_CORE_INI_CFG_OFFSET},
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{"CORES_INI_STATUS ", HPRE_CORE_INI_STATUS_OFFSET},
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{"CORES_HTBT_WARN ", HPRE_CORE_HTBT_WARN_OFFSET},
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{"CORES_IS_SCHD ", HPRE_CORE_IS_SCHD_OFFSET},
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};
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static struct debugfs_reg32 hpre_com_dfx_regs[] = {
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{"READ_CLR_EN ", HPRE_CTRL_CNT_CLR_CE},
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{"AXQOS ", HPRE_VFG_AXQOS},
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{"AWUSR_CFG ", HPRE_AWUSR_FP_CFG},
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{"QM_ARUSR_MCFG1 ", QM_ARUSER_M_CFG_1},
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{"QM_AWUSR_MCFG1 ", QM_AWUSER_M_CFG_1},
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{"BD_ENDIAN ", HPRE_BD_ENDIAN},
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{"ECC_CHECK_CTRL ", HPRE_ECC_BYPASS},
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{"RAS_INT_WIDTH ", HPRE_RAS_WIDTH_CFG},
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{"POISON_BYPASS ", HPRE_POISON_BYPASS},
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{"BD_ARUSER ", HPRE_BD_ARUSR_CFG},
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{"BD_AWUSER ", HPRE_BD_AWUSR_CFG},
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{"DATA_ARUSER ", HPRE_DATA_RUSER_CFG},
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{"DATA_AWUSER ", HPRE_DATA_WUSER_CFG},
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{"INT_STATUS ", HPRE_INT_STATUS},
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};
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static int hpre_pf_q_num_set(const char *val, const struct kernel_param *kp)
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{
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struct pci_dev *pdev;
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@ -284,6 +328,27 @@ static int hpre_set_user_domain_and_cache(struct hpre *hpre)
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return ret;
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}
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static void hpre_cnt_regs_clear(struct hisi_qm *qm)
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{
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unsigned long offset;
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int i;
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/* clear current_qm */
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writel(0x0, qm->io_base + QM_DFX_MB_CNT_VF);
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writel(0x0, qm->io_base + QM_DFX_DB_CNT_VF);
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/* clear clusterX/cluster_ctrl */
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for (i = 0; i < HPRE_CLUSTERS_NUM; i++) {
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offset = HPRE_CLSTR_BASE + i * HPRE_CLSTR_ADDR_INTRVL;
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writel(0x0, qm->io_base + offset + HPRE_CLUSTER_INQURY);
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}
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/* clear rdclr_en */
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writel(0x0, qm->io_base + HPRE_CTRL_CNT_CLR_CE);
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hisi_qm_debug_regs_clear(qm);
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}
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static void hpre_hw_error_disable(struct hpre *hpre)
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{
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struct hisi_qm *qm = &hpre->qm;
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@ -303,6 +368,335 @@ static void hpre_hw_error_enable(struct hpre *hpre)
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writel(HPRE_HAC_RAS_FE_ENABLE, qm->io_base + HPRE_RAS_FE_ENB);
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}
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static inline struct hisi_qm *hpre_file_to_qm(struct hpre_debugfs_file *file)
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{
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struct hpre *hpre = container_of(file->debug, struct hpre, debug);
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return &hpre->qm;
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}
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static u32 hpre_current_qm_read(struct hpre_debugfs_file *file)
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{
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struct hisi_qm *qm = hpre_file_to_qm(file);
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return readl(qm->io_base + QM_DFX_MB_CNT_VF);
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}
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static int hpre_current_qm_write(struct hpre_debugfs_file *file, u32 val)
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{
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struct hisi_qm *qm = hpre_file_to_qm(file);
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struct hpre_debug *debug = file->debug;
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struct hpre *hpre = container_of(debug, struct hpre, debug);
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u32 num_vfs = hpre->num_vfs;
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u32 vfq_num, tmp;
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if (val > num_vfs)
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return -EINVAL;
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/* According PF or VF Dev ID to calculation curr_qm_qp_num and store */
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if (val == 0) {
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qm->debug.curr_qm_qp_num = qm->qp_num;
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} else {
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vfq_num = (qm->ctrl_qp_num - qm->qp_num) / num_vfs;
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if (val == num_vfs) {
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qm->debug.curr_qm_qp_num =
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qm->ctrl_qp_num - qm->qp_num - (num_vfs - 1) * vfq_num;
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} else {
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qm->debug.curr_qm_qp_num = vfq_num;
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}
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}
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writel(val, qm->io_base + QM_DFX_MB_CNT_VF);
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writel(val, qm->io_base + QM_DFX_DB_CNT_VF);
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tmp = val |
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(readl(qm->io_base + QM_DFX_SQE_CNT_VF_SQN) & CURRENT_Q_MASK);
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writel(tmp, qm->io_base + QM_DFX_SQE_CNT_VF_SQN);
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tmp = val |
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(readl(qm->io_base + QM_DFX_CQE_CNT_VF_CQN) & CURRENT_Q_MASK);
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writel(tmp, qm->io_base + QM_DFX_CQE_CNT_VF_CQN);
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return 0;
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}
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static u32 hpre_clear_enable_read(struct hpre_debugfs_file *file)
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{
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struct hisi_qm *qm = hpre_file_to_qm(file);
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return readl(qm->io_base + HPRE_CTRL_CNT_CLR_CE) &
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HPRE_CTRL_CNT_CLR_CE_BIT;
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}
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static int hpre_clear_enable_write(struct hpre_debugfs_file *file, u32 val)
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{
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struct hisi_qm *qm = hpre_file_to_qm(file);
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u32 tmp;
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if (val != 1 && val != 0)
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return -EINVAL;
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tmp = (readl(qm->io_base + HPRE_CTRL_CNT_CLR_CE) &
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~HPRE_CTRL_CNT_CLR_CE_BIT) | val;
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writel(tmp, qm->io_base + HPRE_CTRL_CNT_CLR_CE);
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return 0;
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}
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static u32 hpre_cluster_inqry_read(struct hpre_debugfs_file *file)
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{
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struct hisi_qm *qm = hpre_file_to_qm(file);
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int cluster_index = file->index - HPRE_CLUSTER_CTRL;
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unsigned long offset = HPRE_CLSTR_BASE +
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cluster_index * HPRE_CLSTR_ADDR_INTRVL;
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return readl(qm->io_base + offset + HPRE_CLSTR_ADDR_INQRY_RSLT);
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}
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static int hpre_cluster_inqry_write(struct hpre_debugfs_file *file, u32 val)
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{
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struct hisi_qm *qm = hpre_file_to_qm(file);
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int cluster_index = file->index - HPRE_CLUSTER_CTRL;
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unsigned long offset = HPRE_CLSTR_BASE + cluster_index *
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HPRE_CLSTR_ADDR_INTRVL;
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writel(val, qm->io_base + offset + HPRE_CLUSTER_INQURY);
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return 0;
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}
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static ssize_t hpre_ctrl_debug_read(struct file *filp, char __user *buf,
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size_t count, loff_t *pos)
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{
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struct hpre_debugfs_file *file = filp->private_data;
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char tbuf[HPRE_DBGFS_VAL_MAX_LEN];
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u32 val;
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int ret;
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spin_lock_irq(&file->lock);
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switch (file->type) {
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case HPRE_CURRENT_QM:
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val = hpre_current_qm_read(file);
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break;
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case HPRE_CLEAR_ENABLE:
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val = hpre_clear_enable_read(file);
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break;
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case HPRE_CLUSTER_CTRL:
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val = hpre_cluster_inqry_read(file);
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break;
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default:
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spin_unlock_irq(&file->lock);
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return -EINVAL;
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}
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spin_unlock_irq(&file->lock);
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ret = sprintf(tbuf, "%u\n", val);
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return simple_read_from_buffer(buf, count, pos, tbuf, ret);
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}
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static ssize_t hpre_ctrl_debug_write(struct file *filp, const char __user *buf,
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size_t count, loff_t *pos)
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{
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struct hpre_debugfs_file *file = filp->private_data;
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char tbuf[HPRE_DBGFS_VAL_MAX_LEN];
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unsigned long val;
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int len, ret;
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if (*pos != 0)
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return 0;
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if (count >= HPRE_DBGFS_VAL_MAX_LEN)
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return -ENOSPC;
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len = simple_write_to_buffer(tbuf, HPRE_DBGFS_VAL_MAX_LEN - 1,
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pos, buf, count);
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if (len < 0)
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return len;
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tbuf[len] = '\0';
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if (kstrtoul(tbuf, 0, &val))
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return -EFAULT;
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spin_lock_irq(&file->lock);
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switch (file->type) {
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case HPRE_CURRENT_QM:
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ret = hpre_current_qm_write(file, val);
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if (ret)
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goto err_input;
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break;
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case HPRE_CLEAR_ENABLE:
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ret = hpre_clear_enable_write(file, val);
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if (ret)
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goto err_input;
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break;
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case HPRE_CLUSTER_CTRL:
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ret = hpre_cluster_inqry_write(file, val);
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if (ret)
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goto err_input;
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break;
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default:
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ret = -EINVAL;
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goto err_input;
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}
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spin_unlock_irq(&file->lock);
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return count;
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err_input:
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spin_unlock_irq(&file->lock);
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return ret;
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}
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static const struct file_operations hpre_ctrl_debug_fops = {
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.owner = THIS_MODULE,
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.open = simple_open,
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.read = hpre_ctrl_debug_read,
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.write = hpre_ctrl_debug_write,
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};
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static int hpre_create_debugfs_file(struct hpre_debug *dbg, struct dentry *dir,
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enum hpre_ctrl_dbgfs_file type, int indx)
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{
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struct dentry *tmp, *file_dir;
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if (dir)
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file_dir = dir;
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else
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file_dir = dbg->debug_root;
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if (type >= HPRE_DEBUG_FILE_NUM)
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return -EINVAL;
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spin_lock_init(&dbg->files[indx].lock);
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dbg->files[indx].debug = dbg;
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dbg->files[indx].type = type;
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dbg->files[indx].index = indx;
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tmp = debugfs_create_file(hpre_debug_file_name[type], 0600, file_dir,
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dbg->files + indx, &hpre_ctrl_debug_fops);
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if (!tmp)
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return -ENOENT;
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return 0;
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}
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static int hpre_pf_comm_regs_debugfs_init(struct hpre_debug *debug)
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{
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struct hpre *hpre = container_of(debug, struct hpre, debug);
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struct hisi_qm *qm = &hpre->qm;
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struct device *dev = &qm->pdev->dev;
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struct debugfs_regset32 *regset;
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struct dentry *tmp;
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regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL);
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if (!regset)
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return -ENOMEM;
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regset->regs = hpre_com_dfx_regs;
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regset->nregs = ARRAY_SIZE(hpre_com_dfx_regs);
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regset->base = qm->io_base;
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tmp = debugfs_create_regset32("regs", 0444, debug->debug_root, regset);
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if (!tmp)
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return -ENOENT;
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return 0;
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}
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static int hpre_cluster_debugfs_init(struct hpre_debug *debug)
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{
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struct hpre *hpre = container_of(debug, struct hpre, debug);
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struct hisi_qm *qm = &hpre->qm;
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struct device *dev = &qm->pdev->dev;
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char buf[HPRE_DBGFS_VAL_MAX_LEN];
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struct debugfs_regset32 *regset;
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struct dentry *tmp_d, *tmp;
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int i, ret;
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for (i = 0; i < HPRE_CLUSTERS_NUM; i++) {
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sprintf(buf, "cluster%d", i);
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tmp_d = debugfs_create_dir(buf, debug->debug_root);
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if (!tmp_d)
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return -ENOENT;
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regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL);
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if (!regset)
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return -ENOMEM;
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regset->regs = hpre_cluster_dfx_regs;
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regset->nregs = ARRAY_SIZE(hpre_cluster_dfx_regs);
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regset->base = qm->io_base + hpre_cluster_offsets[i];
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tmp = debugfs_create_regset32("regs", 0444, tmp_d, regset);
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if (!tmp)
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return -ENOENT;
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ret = hpre_create_debugfs_file(debug, tmp_d, HPRE_CLUSTER_CTRL,
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i + HPRE_CLUSTER_CTRL);
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if (ret)
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return ret;
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}
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return 0;
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}
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static int hpre_ctrl_debug_init(struct hpre_debug *debug)
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{
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int ret;
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ret = hpre_create_debugfs_file(debug, NULL, HPRE_CURRENT_QM,
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HPRE_CURRENT_QM);
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if (ret)
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return ret;
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ret = hpre_create_debugfs_file(debug, NULL, HPRE_CLEAR_ENABLE,
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HPRE_CLEAR_ENABLE);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = hpre_pf_comm_regs_debugfs_init(debug);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return hpre_cluster_debugfs_init(debug);
|
||||
}
|
||||
|
||||
static int hpre_debugfs_init(struct hpre *hpre)
|
||||
{
|
||||
struct hisi_qm *qm = &hpre->qm;
|
||||
struct device *dev = &qm->pdev->dev;
|
||||
struct dentry *dir;
|
||||
int ret;
|
||||
|
||||
dir = debugfs_create_dir(dev_name(dev), hpre_debugfs_root);
|
||||
if (!dir)
|
||||
return -ENOENT;
|
||||
|
||||
qm->debug.debug_root = dir;
|
||||
|
||||
ret = hisi_qm_debug_init(qm);
|
||||
if (ret)
|
||||
goto failed_to_create;
|
||||
|
||||
if (qm->pdev->device == HPRE_PCI_DEVICE_ID) {
|
||||
hpre->debug.debug_root = dir;
|
||||
ret = hpre_ctrl_debug_init(&hpre->debug);
|
||||
if (ret)
|
||||
goto failed_to_create;
|
||||
}
|
||||
return 0;
|
||||
|
||||
failed_to_create:
|
||||
debugfs_remove_recursive(qm->debug.debug_root);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void hpre_debugfs_exit(struct hpre *hpre)
|
||||
{
|
||||
struct hisi_qm *qm = &hpre->qm;
|
||||
|
||||
debugfs_remove_recursive(qm->debug.debug_root);
|
||||
}
|
||||
|
||||
static int hpre_qm_pre_init(struct hisi_qm *qm, struct pci_dev *pdev)
|
||||
{
|
||||
enum qm_hw_ver rev_id;
|
||||
|
@ -390,6 +784,10 @@ static int hpre_probe(struct pci_dev *pdev, const struct pci_device_id *id)
|
|||
if (ret)
|
||||
goto err_with_err_init;
|
||||
|
||||
ret = hpre_debugfs_init(hpre);
|
||||
if (ret)
|
||||
dev_warn(&pdev->dev, "init debugfs fail!\n");
|
||||
|
||||
hpre_add_to_list(hpre);
|
||||
|
||||
ret = hpre_algs_register();
|
||||
|
@ -529,6 +927,12 @@ static void hpre_remove(struct pci_dev *pdev)
|
|||
return;
|
||||
}
|
||||
}
|
||||
if (qm->fun_type == QM_HW_PF) {
|
||||
hpre_cnt_regs_clear(qm);
|
||||
qm->debug.curr_qm_qp_num = 0;
|
||||
}
|
||||
|
||||
hpre_debugfs_exit(hpre);
|
||||
hisi_qm_stop(qm);
|
||||
if (qm->fun_type == QM_HW_PF)
|
||||
hpre_hw_error_disable(hpre);
|
||||
|
@ -604,13 +1008,32 @@ static struct pci_driver hpre_pci_driver = {
|
|||
.err_handler = &hpre_err_handler,
|
||||
};
|
||||
|
||||
static void hpre_register_debugfs(void)
|
||||
{
|
||||
if (!debugfs_initialized())
|
||||
return;
|
||||
|
||||
hpre_debugfs_root = debugfs_create_dir(hpre_name, NULL);
|
||||
if (IS_ERR_OR_NULL(hpre_debugfs_root))
|
||||
hpre_debugfs_root = NULL;
|
||||
}
|
||||
|
||||
static void hpre_unregister_debugfs(void)
|
||||
{
|
||||
debugfs_remove_recursive(hpre_debugfs_root);
|
||||
}
|
||||
|
||||
static int __init hpre_init(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
hpre_register_debugfs();
|
||||
|
||||
ret = pci_register_driver(&hpre_pci_driver);
|
||||
if (ret)
|
||||
if (ret) {
|
||||
hpre_unregister_debugfs();
|
||||
pr_err("hpre: can't register hisi hpre driver.\n");
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
@ -618,6 +1041,7 @@ static int __init hpre_init(void)
|
|||
static void __exit hpre_exit(void)
|
||||
{
|
||||
pci_unregister_driver(&hpre_pci_driver);
|
||||
hpre_unregister_debugfs();
|
||||
}
|
||||
|
||||
module_init(hpre_init);
|
||||
|
|
Loading…
Reference in New Issue