drm/amdgpu: Move common code to amdgpu_gfx.c
move common code to amdgpu_gfx_enable_kcq,so this function can be shared with gfx8 and gfx9 Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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drivers/gpu/drm/amd/amdgpu
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@ -450,6 +450,53 @@ int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev)
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return amdgpu_ring_test_ring(kiq_ring);
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}
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int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev)
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{
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struct amdgpu_kiq *kiq = &adev->gfx.kiq;
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struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
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uint64_t queue_mask = 0;
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int r, i;
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if (!kiq->pmf || !kiq->pmf->kiq_map_queues || !kiq->pmf->kiq_set_resources)
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return -EINVAL;
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for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) {
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if (!test_bit(i, adev->gfx.mec.queue_bitmap))
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continue;
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/* This situation may be hit in the future if a new HW
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* generation exposes more than 64 queues. If so, the
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* definition of queue_mask needs updating */
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if (WARN_ON(i > (sizeof(queue_mask)*8))) {
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DRM_ERROR("Invalid KCQ enabled: %d\n", i);
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break;
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}
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queue_mask |= (1ull << i);
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}
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DRM_INFO("kiq ring mec %d pipe %d q %d\n", kiq_ring->me, kiq_ring->pipe,
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kiq_ring->queue);
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r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
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adev->gfx.num_compute_rings +
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kiq->pmf->set_resources_size);
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if (r) {
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DRM_ERROR("Failed to lock KIQ (%d).\n", r);
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return r;
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}
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kiq->pmf->kiq_set_resources(kiq_ring, queue_mask);
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for (i = 0; i < adev->gfx.num_compute_rings; i++)
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kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.compute_ring[i]);
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r = amdgpu_ring_test_helper(kiq_ring);
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if (r)
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DRM_ERROR("KCQ enable failed\n");
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return r;
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}
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/* amdgpu_gfx_off_ctrl - Handle gfx off feature enable/disable
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*
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* @adev: amdgpu_device pointer
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@ -354,6 +354,7 @@ int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev,
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unsigned mqd_size);
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void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev);
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int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev);
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int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev);
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void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev);
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void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev);
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