pinctrl: bcm2835: switch to GPIOLIB_IRQCHIP
It should be possible to use the GPIOLIB_IRQCHIP helper library with the BCM2835 driver since it is a pretty straight forward cascaded irqchip. The only difference from other drivers is that the BCM2835 has several banks for a single gpiochip, and each bank has a separate IRQ line. Instead of creating one gpiochip per bank, a single gpiochip covers all banks GPIO lines. This makes it necessary to resolve the bank ID in the IRQ handler. The GPIOLIB_IRQCHIP allows several IRQs to be cascaded off the same gpiochip by calling gpiochip_set_chained_irqchip() repeatedly, but we have been a bit short on examples for how this should be handled in practice, so this is intended as an example of how this can be achieved. The old code did not model the chip as a chained interrupt handler, but this patch also rectifies that situation. Cc: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Stefan Wahren <stefan.wahren@i2se.com> Tested-by: Eric Anholt <eric@anholt.net> Acked-by: Eric Anholt <eric@anholt.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Linus Walleij
parent
1ff91f0ae3
commit
85ae9e512f
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@ -20,6 +20,7 @@ config PINCTRL_BCM2835
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bool
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select PINMUX
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select PINCONF
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select GPIOLIB_IRQCHIP
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config PINCTRL_IPROC_GPIO
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bool "Broadcom iProc GPIO (with PINCONF) driver"
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@ -24,11 +24,9 @@
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/gpio/driver.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/irqdesc.h>
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#include <linux/irqdomain.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/of.h>
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@ -87,11 +85,6 @@ enum bcm2835_pinconf_pull {
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#define BCM2835_PINCONF_UNPACK_PARAM(_conf_) ((_conf_) >> 16)
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#define BCM2835_PINCONF_UNPACK_ARG(_conf_) ((_conf_) & 0xffff)
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struct bcm2835_gpio_irqdata {
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struct bcm2835_pinctrl *pc;
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int irqgroup;
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};
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struct bcm2835_pinctrl {
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struct device *dev;
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void __iomem *base;
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@ -102,16 +95,13 @@ struct bcm2835_pinctrl {
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unsigned int irq_type[BCM2835_NUM_GPIOS];
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struct pinctrl_dev *pctl_dev;
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struct irq_domain *irq_domain;
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struct gpio_chip gpio_chip;
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struct pinctrl_gpio_range gpio_range;
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struct bcm2835_gpio_irqdata irq_data[BCM2835_NUM_IRQS];
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int irq_group[BCM2835_NUM_IRQS];
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spinlock_t irq_lock[BCM2835_NUM_BANKS];
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};
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static struct lock_class_key gpio_lock_class;
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/* pins are just named GPIO0..GPIO53 */
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#define BCM2835_GPIO_PIN(a) PINCTRL_PIN(a, "gpio" #a)
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static struct pinctrl_pin_desc bcm2835_gpio_pins[] = {
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@ -369,13 +359,6 @@ static int bcm2835_gpio_direction_output(struct gpio_chip *chip,
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return pinctrl_gpio_direction_output(chip->base + offset);
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}
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static int bcm2835_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
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{
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struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
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return irq_linear_revmap(pc->irq_domain, offset);
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}
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static struct gpio_chip bcm2835_gpio_chip = {
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.label = MODULE_NAME,
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.owner = THIS_MODULE,
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@ -386,14 +369,13 @@ static struct gpio_chip bcm2835_gpio_chip = {
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.get_direction = bcm2835_gpio_get_direction,
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.get = bcm2835_gpio_get,
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.set = bcm2835_gpio_set,
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.to_irq = bcm2835_gpio_to_irq,
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.base = -1,
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.ngpio = BCM2835_NUM_GPIOS,
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.can_sleep = false,
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};
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static int bcm2835_gpio_irq_handle_bank(struct bcm2835_pinctrl *pc,
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unsigned int bank, u32 mask)
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static void bcm2835_gpio_irq_handle_bank(struct bcm2835_pinctrl *pc,
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unsigned int bank, u32 mask)
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{
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unsigned long events;
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unsigned offset;
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@ -405,34 +387,49 @@ static int bcm2835_gpio_irq_handle_bank(struct bcm2835_pinctrl *pc,
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events &= pc->enabled_irq_map[bank];
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for_each_set_bit(offset, &events, 32) {
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gpio = (32 * bank) + offset;
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/* FIXME: no clue why the code looks up the type here */
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type = pc->irq_type[gpio];
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generic_handle_irq(irq_linear_revmap(pc->irq_domain, gpio));
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generic_handle_irq(irq_linear_revmap(pc->gpio_chip.irqdomain,
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gpio));
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}
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return (events != 0);
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}
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static irqreturn_t bcm2835_gpio_irq_handler(int irq, void *dev_id)
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static void bcm2835_gpio_irq_handler(struct irq_desc *desc)
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{
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struct bcm2835_gpio_irqdata *irqdata = dev_id;
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struct bcm2835_pinctrl *pc = irqdata->pc;
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int handled = 0;
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struct gpio_chip *chip = irq_desc_get_handler_data(desc);
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struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
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struct irq_chip *host_chip = irq_desc_get_chip(desc);
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int irq = irq_desc_get_irq(desc);
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int group;
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int i;
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switch (irqdata->irqgroup) {
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for (i = 0; i < ARRAY_SIZE(pc->irq); i++) {
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if (pc->irq[i] == irq) {
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group = pc->irq_group[i];
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break;
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}
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}
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/* This should not happen, every IRQ has a bank */
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if (i == ARRAY_SIZE(pc->irq))
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BUG();
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chained_irq_enter(host_chip, desc);
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switch (group) {
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case 0: /* IRQ0 covers GPIOs 0-27 */
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handled = bcm2835_gpio_irq_handle_bank(pc, 0, 0x0fffffff);
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bcm2835_gpio_irq_handle_bank(pc, 0, 0x0fffffff);
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break;
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case 1: /* IRQ1 covers GPIOs 28-45 */
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handled = bcm2835_gpio_irq_handle_bank(pc, 0, 0xf0000000) |
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bcm2835_gpio_irq_handle_bank(pc, 1, 0x00003fff);
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bcm2835_gpio_irq_handle_bank(pc, 0, 0xf0000000);
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bcm2835_gpio_irq_handle_bank(pc, 1, 0x00003fff);
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break;
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case 2: /* IRQ2 covers GPIOs 46-53 */
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handled = bcm2835_gpio_irq_handle_bank(pc, 1, 0x003fc000);
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bcm2835_gpio_irq_handle_bank(pc, 1, 0x003fc000);
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break;
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}
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return handled ? IRQ_HANDLED : IRQ_NONE;
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chained_irq_exit(host_chip, desc);
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}
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static inline void __bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
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@ -478,7 +475,8 @@ static void bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
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static void bcm2835_gpio_irq_enable(struct irq_data *data)
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{
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struct bcm2835_pinctrl *pc = irq_data_get_irq_chip_data(data);
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struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
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struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
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unsigned gpio = irqd_to_hwirq(data);
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unsigned offset = GPIO_REG_SHIFT(gpio);
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unsigned bank = GPIO_REG_OFFSET(gpio);
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@ -492,7 +490,8 @@ static void bcm2835_gpio_irq_enable(struct irq_data *data)
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static void bcm2835_gpio_irq_disable(struct irq_data *data)
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{
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struct bcm2835_pinctrl *pc = irq_data_get_irq_chip_data(data);
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struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
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struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
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unsigned gpio = irqd_to_hwirq(data);
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unsigned offset = GPIO_REG_SHIFT(gpio);
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unsigned bank = GPIO_REG_OFFSET(gpio);
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@ -598,7 +597,8 @@ static int __bcm2835_gpio_irq_set_type_enabled(struct bcm2835_pinctrl *pc,
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static int bcm2835_gpio_irq_set_type(struct irq_data *data, unsigned int type)
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{
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struct bcm2835_pinctrl *pc = irq_data_get_irq_chip_data(data);
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struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
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struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
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unsigned gpio = irqd_to_hwirq(data);
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unsigned offset = GPIO_REG_SHIFT(gpio);
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unsigned bank = GPIO_REG_OFFSET(gpio);
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@ -624,7 +624,8 @@ static int bcm2835_gpio_irq_set_type(struct irq_data *data, unsigned int type)
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static void bcm2835_gpio_irq_ack(struct irq_data *data)
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{
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struct bcm2835_pinctrl *pc = irq_data_get_irq_chip_data(data);
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struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
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struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
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unsigned gpio = irqd_to_hwirq(data);
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bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
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@ -667,10 +668,11 @@ static void bcm2835_pctl_pin_dbg_show(struct pinctrl_dev *pctldev,
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unsigned offset)
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{
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struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
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struct gpio_chip *chip = &pc->gpio_chip;
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enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
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const char *fname = bcm2835_functions[fsel];
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int value = bcm2835_gpio_get_bit(pc, GPLEV0, offset);
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int irq = irq_find_mapping(pc->irq_domain, offset);
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int irq = irq_find_mapping(chip->irqdomain, offset);
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seq_printf(s, "function %s in %s; irq %d (%s)",
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fname, value ? "hi" : "lo",
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@ -1016,21 +1018,6 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev)
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pc->gpio_chip.parent = dev;
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pc->gpio_chip.of_node = np;
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pc->irq_domain = irq_domain_add_linear(np, BCM2835_NUM_GPIOS,
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&irq_domain_simple_ops, NULL);
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if (!pc->irq_domain) {
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dev_err(dev, "could not create IRQ domain\n");
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return -ENOMEM;
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}
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for (i = 0; i < BCM2835_NUM_GPIOS; i++) {
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int irq = irq_create_mapping(pc->irq_domain, i);
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irq_set_lockdep_class(irq, &gpio_lock_class);
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irq_set_chip_and_handler(irq, &bcm2835_gpio_irq_chip,
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handle_level_irq);
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irq_set_chip_data(irq, pc);
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}
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for (i = 0; i < BCM2835_NUM_BANKS; i++) {
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unsigned long events;
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unsigned offset;
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@ -1051,34 +1038,35 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev)
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spin_lock_init(&pc->irq_lock[i]);
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}
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for (i = 0; i < BCM2835_NUM_IRQS; i++) {
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int len;
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char *name;
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pc->irq[i] = irq_of_parse_and_map(np, i);
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pc->irq_data[i].pc = pc;
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pc->irq_data[i].irqgroup = i;
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len = strlen(dev_name(pc->dev)) + 16;
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name = devm_kzalloc(pc->dev, len, GFP_KERNEL);
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if (!name)
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return -ENOMEM;
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snprintf(name, len, "%s:bank%d", dev_name(pc->dev), i);
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err = devm_request_irq(dev, pc->irq[i],
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bcm2835_gpio_irq_handler, IRQF_SHARED,
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name, &pc->irq_data[i]);
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if (err) {
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dev_err(dev, "unable to request IRQ %d\n", pc->irq[i]);
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return err;
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}
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}
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err = gpiochip_add_data(&pc->gpio_chip, pc);
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if (err) {
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dev_err(dev, "could not add GPIO chip\n");
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return err;
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}
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err = gpiochip_irqchip_add(&pc->gpio_chip, &bcm2835_gpio_irq_chip,
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0, handle_level_irq, IRQ_TYPE_NONE);
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if (err) {
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dev_info(dev, "could not add irqchip\n");
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return err;
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}
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for (i = 0; i < BCM2835_NUM_IRQS; i++) {
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pc->irq[i] = irq_of_parse_and_map(np, i);
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pc->irq_group[i] = i;
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/*
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* Use the same handler for all groups: this is necessary
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* since we use one gpiochip to cover all lines - the
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* irq handler then needs to figure out which group and
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* bank that was firing the IRQ and look up the per-group
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* and bank data.
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*/
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gpiochip_set_chained_irqchip(&pc->gpio_chip,
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&bcm2835_gpio_irq_chip,
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pc->irq[i],
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bcm2835_gpio_irq_handler);
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}
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pc->pctl_dev = devm_pinctrl_register(dev, &bcm2835_pinctrl_desc, pc);
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if (IS_ERR(pc->pctl_dev)) {
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gpiochip_remove(&pc->gpio_chip);
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