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tools/testing/nvdimm: simulate multiple flush hints per-dimm 

Sample nfit data to test the kernel's handling of the multiple
flush-hint case.

Signed-off-by: Dan Williams <dan.j.williams@intel.com>
This commit is contained in:
Dan Williams 2016-06-02 16:27:21 -07:00
parent e5ae3b252c
commit 85d3fa02e4
1 changed files with 33 additions and 22 deletions
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55
tools/testing/nvdimm/test/nfit.c
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@ -98,6 +98,7 @@
enum { enum {
NUM_PM = 3, NUM_PM = 3,
NUM_DCR = 5, NUM_DCR = 5,
NUM_HINTS = 8,
NUM_BDW = NUM_DCR, NUM_BDW = NUM_DCR,
NUM_SPA = NUM_PM + NUM_DCR + NUM_BDW, NUM_SPA = NUM_PM + NUM_DCR + NUM_BDW,
NUM_MEM = NUM_DCR + NUM_BDW + 2 /* spa0 iset */ + 4 /* spa1 iset */, NUM_MEM = NUM_DCR + NUM_BDW + 2 /* spa0 iset */ + 4 /* spa1 iset */,
@ -569,7 +570,8 @@ static int nfit_test0_alloc(struct nfit_test *t)
+ offsetof(struct acpi_nfit_control_region, + offsetof(struct acpi_nfit_control_region,
window_size) * NUM_DCR window_size) * NUM_DCR
+ sizeof(struct acpi_nfit_data_region) * NUM_BDW + sizeof(struct acpi_nfit_data_region) * NUM_BDW
+ sizeof(struct acpi_nfit_flush_address) * NUM_DCR; + (sizeof(struct acpi_nfit_flush_address)
+ sizeof(u64) * NUM_HINTS) * NUM_DCR;
int i; int i;
t->nfit_buf = test_alloc(t, nfit_size, &t->nfit_dma); t->nfit_buf = test_alloc(t, nfit_size, &t->nfit_dma);
@ -599,7 +601,8 @@ static int nfit_test0_alloc(struct nfit_test *t)
return -ENOMEM; return -ENOMEM;
sprintf(t->label[i], "label%d", i); sprintf(t->label[i], "label%d", i);
t->flush[i] = test_alloc(t, 8, &t->flush_dma[i]); t->flush[i] = test_alloc(t, sizeof(u64) * NUM_HINTS,
&t->flush_dma[i]);
if (!t->flush[i]) if (!t->flush[i])
return -ENOMEM; return -ENOMEM;
} }
@ -633,6 +636,8 @@ static int nfit_test1_alloc(struct nfit_test *t)
static void nfit_test0_setup(struct nfit_test *t) static void nfit_test0_setup(struct nfit_test *t)
{ {
const int flush_hint_size = sizeof(struct acpi_nfit_flush_address)
+ (sizeof(u64) * NUM_HINTS);
struct acpi_nfit_desc *acpi_desc; struct acpi_nfit_desc *acpi_desc;
struct acpi_nfit_memory_map *memdev; struct acpi_nfit_memory_map *memdev;
void *nfit_buf = t->nfit_buf; void *nfit_buf = t->nfit_buf;
@ -640,7 +645,7 @@ static void nfit_test0_setup(struct nfit_test *t)
struct acpi_nfit_control_region *dcr; struct acpi_nfit_control_region *dcr;
struct acpi_nfit_data_region *bdw; struct acpi_nfit_data_region *bdw;
struct acpi_nfit_flush_address *flush; struct acpi_nfit_flush_address *flush;
unsigned int offset; unsigned int offset, i;
/* /*
* spa0 (interleave first half of dimm0 and dimm1, note storage * spa0 (interleave first half of dimm0 and dimm1, note storage
@ -1126,37 +1131,41 @@ static void nfit_test0_setup(struct nfit_test *t)
/* flush0 (dimm0) */ /* flush0 (dimm0) */
flush = nfit_buf + offset; flush = nfit_buf + offset;
flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS; flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS;
flush->header.length = sizeof(struct acpi_nfit_flush_address); flush->header.length = flush_hint_size;
flush->device_handle = handle[0]; flush->device_handle = handle[0];
flush->hint_count = 1; flush->hint_count = NUM_HINTS;
flush->hint_address[0] = t->flush_dma[0]; for (i = 0; i < NUM_HINTS; i++)
flush->hint_address[i] = t->flush_dma[0] + i * sizeof(u64);
/* flush1 (dimm1) */ /* flush1 (dimm1) */
flush = nfit_buf + offset + sizeof(struct acpi_nfit_flush_address) * 1; flush = nfit_buf + offset + flush_hint_size * 1;
flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS; flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS;
flush->header.length = sizeof(struct acpi_nfit_flush_address); flush->header.length = flush_hint_size;
flush->device_handle = handle[1]; flush->device_handle = handle[1];
flush->hint_count = 1; flush->hint_count = NUM_HINTS;
flush->hint_address[0] = t->flush_dma[1]; for (i = 0; i < NUM_HINTS; i++)
flush->hint_address[i] = t->flush_dma[1] + i * sizeof(u64);
/* flush2 (dimm2) */ /* flush2 (dimm2) */
flush = nfit_buf + offset + sizeof(struct acpi_nfit_flush_address) * 2; flush = nfit_buf + offset + flush_hint_size * 2;
flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS; flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS;
flush->header.length = sizeof(struct acpi_nfit_flush_address); flush->header.length = flush_hint_size;
flush->device_handle = handle[2]; flush->device_handle = handle[2];
flush->hint_count = 1; flush->hint_count = NUM_HINTS;
flush->hint_address[0] = t->flush_dma[2]; for (i = 0; i < NUM_HINTS; i++)
flush->hint_address[i] = t->flush_dma[2] + i * sizeof(u64);
/* flush3 (dimm3) */ /* flush3 (dimm3) */
flush = nfit_buf + offset + sizeof(struct acpi_nfit_flush_address) * 3; flush = nfit_buf + offset + flush_hint_size * 3;
flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS; flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS;
flush->header.length = sizeof(struct acpi_nfit_flush_address); flush->header.length = flush_hint_size;
flush->device_handle = handle[3]; flush->device_handle = handle[3];
flush->hint_count = 1; flush->hint_count = NUM_HINTS;
flush->hint_address[0] = t->flush_dma[3]; for (i = 0; i < NUM_HINTS; i++)
flush->hint_address[i] = t->flush_dma[3] + i * sizeof(u64);
if (t->setup_hotplug) { if (t->setup_hotplug) {
offset = offset + sizeof(struct acpi_nfit_flush_address) * 4; offset = offset + flush_hint_size * 4;
/* dcr-descriptor4: blk */ /* dcr-descriptor4: blk */
dcr = nfit_buf + offset; dcr = nfit_buf + offset;
dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION; dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
@ -1285,10 +1294,12 @@ static void nfit_test0_setup(struct nfit_test *t)
/* flush3 (dimm4) */ /* flush3 (dimm4) */
flush = nfit_buf + offset; flush = nfit_buf + offset;
flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS; flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS;
flush->header.length = sizeof(struct acpi_nfit_flush_address); flush->header.length = flush_hint_size;
flush->device_handle = handle[4]; flush->device_handle = handle[4];
flush->hint_count = 1; flush->hint_count = NUM_HINTS;
flush->hint_address[0] = t->flush_dma[4]; for (i = 0; i < NUM_HINTS; i++)
flush->hint_address[i] = t->flush_dma[4]
+ i * sizeof(u64);
} }
post_ars_status(&t->ars_state, t->spa_set_dma[0], SPA0_SIZE); post_ars_status(&t->ars_state, t->spa_set_dma[0], SPA0_SIZE);