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drm/exynos/decon5433: fix timing registers writes 

All timing registers should contain values decreased by one.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
This commit is contained in:
Andrzej Hajda 2015-10-20 11:22:36 +02:00 committed by Inki Dae
parent 4f54f21cd6
commit 85de275ad9
1 changed files with 9 additions and 9 deletions
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18
drivers/gpu/drm/exynos/exynos5433_drm_decon.c
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@ -104,7 +104,7 @@ static void decon_setup_trigger(struct decon_context *ctx)
static void decon_commit(struct exynos_drm_crtc *crtc) static void decon_commit(struct exynos_drm_crtc *crtc)
{ {
struct decon_context *ctx = crtc->ctx; struct decon_context *ctx = crtc->ctx;
struct drm_display_mode *mode = &crtc->base.mode; struct drm_display_mode *m = &crtc->base.mode;
u32 val; u32 val;
if (ctx->suspended) if (ctx->suspended)
@ -122,29 +122,29 @@ static void decon_commit(struct exynos_drm_crtc *crtc)
val |= VIDOUT_RGB_IF; val |= VIDOUT_RGB_IF;
writel(val, ctx->addr + DECON_VIDOUTCON0); writel(val, ctx->addr + DECON_VIDOUTCON0);
val = VIDTCON2_LINEVAL(mode->vdisplay - 1) | val = VIDTCON2_LINEVAL(m->vdisplay - 1) |
VIDTCON2_HOZVAL(mode->hdisplay - 1); VIDTCON2_HOZVAL(m->hdisplay - 1);
writel(val, ctx->addr + DECON_VIDTCON2); writel(val, ctx->addr + DECON_VIDTCON2);
if (!ctx->i80_if) { if (!ctx->i80_if) {
val = VIDTCON00_VBPD_F( val = VIDTCON00_VBPD_F(
mode->crtc_vtotal - mode->crtc_vsync_end) | m->crtc_vtotal - m->crtc_vsync_end - 1) |
VIDTCON00_VFPD_F( VIDTCON00_VFPD_F(
mode->crtc_vsync_start - mode->crtc_vdisplay); m->crtc_vsync_start - m->crtc_vdisplay - 1);
writel(val, ctx->addr + DECON_VIDTCON00); writel(val, ctx->addr + DECON_VIDTCON00);
val = VIDTCON01_VSPW_F( val = VIDTCON01_VSPW_F(
mode->crtc_vsync_end - mode->crtc_vsync_start); m->crtc_vsync_end - m->crtc_vsync_start - 1);
writel(val, ctx->addr + DECON_VIDTCON01); writel(val, ctx->addr + DECON_VIDTCON01);
val = VIDTCON10_HBPD_F( val = VIDTCON10_HBPD_F(
mode->crtc_htotal - mode->crtc_hsync_end) | m->crtc_htotal - m->crtc_hsync_end - 1) |
VIDTCON10_HFPD_F( VIDTCON10_HFPD_F(
mode->crtc_hsync_start - mode->crtc_hdisplay); m->crtc_hsync_start - m->crtc_hdisplay - 1);
writel(val, ctx->addr + DECON_VIDTCON10); writel(val, ctx->addr + DECON_VIDTCON10);
val = VIDTCON11_HSPW_F( val = VIDTCON11_HSPW_F(
mode->crtc_hsync_end - mode->crtc_hsync_start); m->crtc_hsync_end - m->crtc_hsync_start - 1);
writel(val, ctx->addr + DECON_VIDTCON11); writel(val, ctx->addr + DECON_VIDTCON11);
} }