mmc: sdhci: host: add new f_sdh30
This patch adds new host controller driver for Fujitsu SDHCI controller f_sdh30. Signed-off-by: Vincent Yang <Vincent.Yang@tw.fujitsu.com> Signed-off-by: Andy Green <andy.green@linaro.org> Signed-off-by: Tetsuya Takinishi <t.takinishi@jp.fujitsu.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
Vincent Yang
Ulf Hansson
parent
d3fc5d71ac
commit
87a507459f
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@ -0,0 +1,30 @@
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* Fujitsu SDHCI controller
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This file documents differences between the core properties in mmc.txt
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and the properties used by the sdhci_f_sdh30 driver.
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Required properties:
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- compatible: "fujitsu,mb86s70-sdhci-3.0"
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- clocks: Must contain an entry for each entry in clock-names. It is a
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list of phandles and clock-specifier pairs.
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See ../clocks/clock-bindings.txt for details.
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- clock-names: Should contain the following two entries:
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"iface" - clock used for sdhci interface
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"core" - core clock for sdhci controller
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Optional properties:
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- vqmmc-supply: phandle to the regulator device tree node, mentioned
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as the VCCQ/VDD_IO supply in the eMMC/SD specs.
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Example:
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sdhci1: mmc@36600000 {
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compatible = "fujitsu,mb86s70-sdhci-3.0";
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reg = <0 0x36600000 0x1000>;
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interrupts = <0 172 0x4>,
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<0 173 0x4>;
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bus-width = <4>;
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vqmmc-supply = <&vccq_sdhci1>;
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clocks = <&clock 2 2 0>, <&clock 2 3 0>;
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clock-names = "iface", "core";
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};
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@ -292,6 +292,17 @@ config MMC_SDHCI_BCM2835
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If unsure, say N.
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config MMC_SDHCI_F_SDH30
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tristate "SDHCI support for Fujitsu Semiconductor F_SDH30"
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depends on MMC_SDHCI_PLTFM
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depends on OF
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help
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This selects the Secure Digital Host Controller Interface (SDHCI)
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Needed by some Fujitsu SoC for MMC / SD / SDIO support.
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If you have a controller with this interface, say Y or M here.
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If unsure, say N.
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config MMC_MOXART
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tristate "MOXART SD/MMC Host Controller support"
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depends on ARCH_MOXART && MMC
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@ -16,6 +16,7 @@ obj-$(CONFIG_MMC_SDHCI_PXAV3) += sdhci-pxav3.o
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obj-$(CONFIG_MMC_SDHCI_PXAV2) += sdhci-pxav2.o
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obj-$(CONFIG_MMC_SDHCI_S3C) += sdhci-s3c.o
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obj-$(CONFIG_MMC_SDHCI_SIRF) += sdhci-sirf.o
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obj-$(CONFIG_MMC_SDHCI_F_SDH30) += sdhci_f_sdh30.o
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obj-$(CONFIG_MMC_SDHCI_SPEAR) += sdhci-spear.o
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obj-$(CONFIG_MMC_WBSD) += wbsd.o
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obj-$(CONFIG_MMC_AU1X) += au1xmmc.o
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@ -0,0 +1,237 @@
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/*
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* linux/drivers/mmc/host/sdhci_f_sdh30.c
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*
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* Copyright (C) 2013 - 2015 Fujitsu Semiconductor, Ltd
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* Vincent Yang <vincent.yang@tw.fujitsu.com>
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* Copyright (C) 2015 Linaro Ltd Andy Green <andy.green@linaro.org>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, version 2 of the License.
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*/
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#include <linux/err.h>
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#include <linux/delay.h>
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#include <linux/module.h>
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#include <linux/clk.h>
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#include "sdhci-pltfm.h"
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/* F_SDH30 extended Controller registers */
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#define F_SDH30_AHB_CONFIG 0x100
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#define F_SDH30_AHB_BIGED 0x00000040
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#define F_SDH30_BUSLOCK_DMA 0x00000020
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#define F_SDH30_BUSLOCK_EN 0x00000010
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#define F_SDH30_SIN 0x00000008
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#define F_SDH30_AHB_INCR_16 0x00000004
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#define F_SDH30_AHB_INCR_8 0x00000002
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#define F_SDH30_AHB_INCR_4 0x00000001
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#define F_SDH30_TUNING_SETTING 0x108
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#define F_SDH30_CMD_CHK_DIS 0x00010000
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#define F_SDH30_IO_CONTROL2 0x114
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#define F_SDH30_CRES_O_DN 0x00080000
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#define F_SDH30_MSEL_O_1_8 0x00040000
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#define F_SDH30_ESD_CONTROL 0x124
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#define F_SDH30_EMMC_RST 0x00000002
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#define F_SDH30_EMMC_HS200 0x01000000
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#define F_SDH30_CMD_DAT_DELAY 0x200
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#define F_SDH30_MIN_CLOCK 400000
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struct f_sdhost_priv {
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struct clk *clk_iface;
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struct clk *clk;
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u32 vendor_hs200;
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struct device *dev;
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};
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void sdhci_f_sdh30_soft_voltage_switch(struct sdhci_host *host)
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{
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struct f_sdhost_priv *priv = sdhci_priv(host);
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u32 ctrl = 0;
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usleep_range(2500, 3000);
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ctrl = sdhci_readl(host, F_SDH30_IO_CONTROL2);
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ctrl |= F_SDH30_CRES_O_DN;
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sdhci_writel(host, ctrl, F_SDH30_IO_CONTROL2);
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ctrl |= F_SDH30_MSEL_O_1_8;
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sdhci_writel(host, ctrl, F_SDH30_IO_CONTROL2);
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ctrl &= ~F_SDH30_CRES_O_DN;
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sdhci_writel(host, ctrl, F_SDH30_IO_CONTROL2);
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usleep_range(2500, 3000);
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if (priv->vendor_hs200) {
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dev_info(priv->dev, "%s: setting hs200\n", __func__);
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ctrl = sdhci_readl(host, F_SDH30_ESD_CONTROL);
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ctrl |= priv->vendor_hs200;
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sdhci_writel(host, ctrl, F_SDH30_ESD_CONTROL);
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}
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ctrl = sdhci_readl(host, F_SDH30_TUNING_SETTING);
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ctrl |= F_SDH30_CMD_CHK_DIS;
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sdhci_writel(host, ctrl, F_SDH30_TUNING_SETTING);
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}
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unsigned int sdhci_f_sdh30_get_min_clock(struct sdhci_host *host)
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{
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return F_SDH30_MIN_CLOCK;
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}
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void sdhci_f_sdh30_reset(struct sdhci_host *host, u8 mask)
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{
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if (sdhci_readw(host, SDHCI_CLOCK_CONTROL) == 0)
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sdhci_writew(host, 0xBC01, SDHCI_CLOCK_CONTROL);
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sdhci_reset(host, mask);
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}
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static const struct sdhci_ops sdhci_f_sdh30_ops = {
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.voltage_switch = sdhci_f_sdh30_soft_voltage_switch,
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.get_min_clock = sdhci_f_sdh30_get_min_clock,
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.reset = sdhci_f_sdh30_reset,
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.set_clock = sdhci_set_clock,
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.set_bus_width = sdhci_set_bus_width,
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.set_uhs_signaling = sdhci_set_uhs_signaling,
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};
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static int sdhci_f_sdh30_probe(struct platform_device *pdev)
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{
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struct sdhci_host *host;
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struct device *dev = &pdev->dev;
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struct resource *res;
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int irq, ctrl = 0, ret = 0;
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struct f_sdhost_priv *priv;
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u32 reg = 0;
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irq = platform_get_irq(pdev, 0);
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if (irq < 0) {
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dev_err(dev, "%s: no irq specified\n", __func__);
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return irq;
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}
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host = sdhci_alloc_host(dev, sizeof(struct sdhci_host) +
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sizeof(struct f_sdhost_priv));
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if (IS_ERR(host))
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return PTR_ERR(host);
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priv = sdhci_priv(host);
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priv->dev = dev;
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host->quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
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SDHCI_QUIRK_INVERTED_WRITE_PROTECT;
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host->quirks2 = SDHCI_QUIRK2_SUPPORT_SINGLE |
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SDHCI_QUIRK2_TUNING_WORK_AROUND;
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ret = mmc_of_parse(host->mmc);
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if (ret)
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goto err;
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platform_set_drvdata(pdev, host);
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sdhci_get_of_property(pdev);
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host->hw_name = "f_sdh30";
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host->ops = &sdhci_f_sdh30_ops;
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host->irq = irq;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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host->ioaddr = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(host->ioaddr)) {
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ret = PTR_ERR(host);
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goto err;
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}
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priv->clk_iface = devm_clk_get(&pdev->dev, "iface");
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if (IS_ERR(priv->clk_iface)) {
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ret = PTR_ERR(priv->clk_iface);
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goto err;
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}
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ret = clk_prepare_enable(priv->clk_iface);
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if (ret)
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goto err;
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priv->clk = devm_clk_get(&pdev->dev, "core");
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if (IS_ERR(priv->clk)) {
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ret = PTR_ERR(priv->clk);
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goto err_clk;
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}
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ret = clk_prepare_enable(priv->clk);
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if (ret)
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goto err_clk;
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/* init vendor specific regs */
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ctrl = sdhci_readw(host, F_SDH30_AHB_CONFIG);
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ctrl |= F_SDH30_SIN | F_SDH30_AHB_INCR_16 | F_SDH30_AHB_INCR_8 |
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F_SDH30_AHB_INCR_4;
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ctrl &= ~(F_SDH30_AHB_BIGED | F_SDH30_BUSLOCK_EN);
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sdhci_writew(host, ctrl, F_SDH30_AHB_CONFIG);
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reg = sdhci_readl(host, F_SDH30_ESD_CONTROL);
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sdhci_writel(host, reg & ~F_SDH30_EMMC_RST, F_SDH30_ESD_CONTROL);
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msleep(20);
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sdhci_writel(host, reg | F_SDH30_EMMC_RST, F_SDH30_ESD_CONTROL);
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reg = sdhci_readl(host, SDHCI_CAPABILITIES);
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if (reg & SDHCI_CAN_DO_8BIT)
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priv->vendor_hs200 = F_SDH30_EMMC_HS200;
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ret = sdhci_add_host(host);
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if (ret)
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goto err_add_host;
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return 0;
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err_add_host:
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clk_disable_unprepare(priv->clk);
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err_clk:
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clk_disable_unprepare(priv->clk_iface);
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err:
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sdhci_free_host(host);
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return ret;
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}
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static int sdhci_f_sdh30_remove(struct platform_device *pdev)
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{
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struct sdhci_host *host = platform_get_drvdata(pdev);
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struct f_sdhost_priv *priv = sdhci_priv(host);
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sdhci_remove_host(host, readl(host->ioaddr + SDHCI_INT_STATUS) ==
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0xffffffff);
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clk_disable_unprepare(priv->clk_iface);
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clk_disable_unprepare(priv->clk);
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sdhci_free_host(host);
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platform_set_drvdata(pdev, NULL);
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return 0;
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}
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static const struct of_device_id f_sdh30_dt_ids[] = {
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{ .compatible = "fujitsu,mb86s70-sdhci-3.0" },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, f_sdh30_dt_ids);
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static struct platform_driver sdhci_f_sdh30_driver = {
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.driver = {
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.name = "f_sdh30",
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.of_match_table = f_sdh30_dt_ids,
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.pm = SDHCI_PLTFM_PMOPS,
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},
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.probe = sdhci_f_sdh30_probe,
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.remove = sdhci_f_sdh30_remove,
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};
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module_platform_driver(sdhci_f_sdh30_driver);
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MODULE_DESCRIPTION("F_SDH30 SD Card Controller driver");
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MODULE_LICENSE("GPL v2");
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MODULE_AUTHOR("FUJITSU SEMICONDUCTOR LTD.");
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MODULE_ALIAS("platform:f_sdh30");
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