drm/nouveau/gr/gf100: instantiate and reserve GR falcons
Create instances for the FECS and GPCCS falcons and use the init() and fini() hooks to reserve them for as long as GR controls them. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Alexandre Courbot
Ben Skeggs
parent
0296b5d985
commit
89cd6e2071
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@ -1391,26 +1391,11 @@ gf100_gr_intr(struct nvkm_gr *base)
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}
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static void
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gf100_gr_init_fw(struct gf100_gr *gr, u32 fuc_base,
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gf100_gr_init_fw(struct nvkm_falcon *falcon,
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struct gf100_gr_fuc *code, struct gf100_gr_fuc *data)
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{
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struct nvkm_device *device = gr->base.engine.subdev.device;
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int i;
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nvkm_wr32(device, fuc_base + 0x01c0, 0x01000000);
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for (i = 0; i < data->size / 4; i++)
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nvkm_wr32(device, fuc_base + 0x01c4, data->data[i]);
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nvkm_wr32(device, fuc_base + 0x0180, 0x01000000);
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for (i = 0; i < code->size / 4; i++) {
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if ((i & 0x3f) == 0)
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nvkm_wr32(device, fuc_base + 0x0188, i >> 6);
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nvkm_wr32(device, fuc_base + 0x0184, code->data[i]);
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}
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/* code must be padded to 0x40 words */
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for (; i & 0x3f; i++)
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nvkm_wr32(device, fuc_base + 0x0184, 0);
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nvkm_falcon_load_dmem(falcon, data->data, 0x0, data->size, 0);
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nvkm_falcon_load_imem(falcon, code->data, 0x0, code->size, 0, 0, false);
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}
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static void
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@ -1471,14 +1456,14 @@ gf100_gr_init_ctxctl_ext(struct gf100_gr *gr)
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if (nvkm_secboot_is_managed(sb, NVKM_SECBOOT_FALCON_FECS))
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ret = nvkm_secboot_reset(sb, NVKM_SECBOOT_FALCON_FECS);
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else
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gf100_gr_init_fw(gr, 0x409000, &gr->fuc409c, &gr->fuc409d);
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gf100_gr_init_fw(gr->fecs, &gr->fuc409c, &gr->fuc409d);
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if (ret)
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return ret;
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if (nvkm_secboot_is_managed(sb, NVKM_SECBOOT_FALCON_GPCCS))
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ret = nvkm_secboot_reset(sb, NVKM_SECBOOT_FALCON_GPCCS);
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else
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gf100_gr_init_fw(gr, 0x41a000, &gr->fuc41ac, &gr->fuc41ad);
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gf100_gr_init_fw(gr->gpccs, &gr->fuc41ac, &gr->fuc41ad);
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if (ret)
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return ret;
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@ -1489,14 +1474,9 @@ gf100_gr_init_ctxctl_ext(struct gf100_gr *gr)
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nvkm_wr32(device, 0x41a10c, 0x00000000);
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nvkm_wr32(device, 0x40910c, 0x00000000);
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if (nvkm_secboot_is_managed(sb, NVKM_SECBOOT_FALCON_GPCCS))
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nvkm_secboot_start(sb, NVKM_SECBOOT_FALCON_GPCCS);
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else
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nvkm_wr32(device, 0x41a100, 0x00000002);
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if (nvkm_secboot_is_managed(sb, NVKM_SECBOOT_FALCON_FECS))
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nvkm_secboot_start(sb, NVKM_SECBOOT_FALCON_FECS);
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else
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nvkm_wr32(device, 0x409100, 0x00000002);
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nvkm_falcon_start(gr->gpccs);
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nvkm_falcon_start(gr->fecs);
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if (nvkm_msec(device, 2000,
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if (nvkm_rd32(device, 0x409800) & 0x00000001)
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break;
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@ -1586,7 +1566,6 @@ gf100_gr_init_ctxctl_int(struct gf100_gr *gr)
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const struct gf100_grctx_func *grctx = gr->func->grctx;
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struct nvkm_subdev *subdev = &gr->base.engine.subdev;
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struct nvkm_device *device = subdev->device;
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int i;
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if (!gr->func->fecs.ucode) {
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return -ENOSYS;
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@ -1594,28 +1573,16 @@ gf100_gr_init_ctxctl_int(struct gf100_gr *gr)
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/* load HUB microcode */
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nvkm_mc_unk260(device, 0);
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nvkm_wr32(device, 0x4091c0, 0x01000000);
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for (i = 0; i < gr->func->fecs.ucode->data.size / 4; i++)
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nvkm_wr32(device, 0x4091c4, gr->func->fecs.ucode->data.data[i]);
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nvkm_wr32(device, 0x409180, 0x01000000);
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for (i = 0; i < gr->func->fecs.ucode->code.size / 4; i++) {
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if ((i & 0x3f) == 0)
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nvkm_wr32(device, 0x409188, i >> 6);
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nvkm_wr32(device, 0x409184, gr->func->fecs.ucode->code.data[i]);
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}
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nvkm_falcon_load_dmem(gr->fecs, gr->func->fecs.ucode->data.data, 0x0,
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gr->func->fecs.ucode->data.size, 0);
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nvkm_falcon_load_imem(gr->fecs, gr->func->fecs.ucode->code.data, 0x0,
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gr->func->fecs.ucode->code.size, 0, 0, false);
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/* load GPC microcode */
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nvkm_wr32(device, 0x41a1c0, 0x01000000);
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for (i = 0; i < gr->func->gpccs.ucode->data.size / 4; i++)
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nvkm_wr32(device, 0x41a1c4, gr->func->gpccs.ucode->data.data[i]);
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nvkm_wr32(device, 0x41a180, 0x01000000);
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for (i = 0; i < gr->func->gpccs.ucode->code.size / 4; i++) {
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if ((i & 0x3f) == 0)
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nvkm_wr32(device, 0x41a188, i >> 6);
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nvkm_wr32(device, 0x41a184, gr->func->gpccs.ucode->code.data[i]);
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}
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nvkm_falcon_load_dmem(gr->gpccs, gr->func->gpccs.ucode->data.data, 0x0,
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gr->func->gpccs.ucode->data.size, 0);
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nvkm_falcon_load_imem(gr->gpccs, gr->func->gpccs.ucode->code.data, 0x0,
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gr->func->gpccs.ucode->code.size, 0, 0, false);
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nvkm_mc_unk260(device, 1);
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/* load register lists */
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@ -1729,10 +1696,32 @@ static int
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gf100_gr_init_(struct nvkm_gr *base)
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{
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struct gf100_gr *gr = gf100_gr(base);
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struct nvkm_subdev *subdev = &base->engine.subdev;
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u32 ret;
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nvkm_pmu_pgob(gr->base.engine.subdev.device->pmu, false);
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ret = nvkm_falcon_get(gr->fecs, subdev);
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if (ret)
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return ret;
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ret = nvkm_falcon_get(gr->gpccs, subdev);
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if (ret)
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return ret;
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return gr->func->init(gr);
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}
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static int
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gf100_gr_fini_(struct nvkm_gr *base, bool suspend)
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{
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struct gf100_gr *gr = gf100_gr(base);
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struct nvkm_subdev *subdev = &gr->base.engine.subdev;
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nvkm_falcon_put(gr->gpccs, subdev);
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nvkm_falcon_put(gr->fecs, subdev);
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return 0;
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}
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void
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gf100_gr_dtor_fw(struct gf100_gr_fuc *fuc)
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{
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@ -1755,6 +1744,9 @@ gf100_gr_dtor(struct nvkm_gr *base)
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gr->func->dtor(gr);
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kfree(gr->data);
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nvkm_falcon_del(&gr->gpccs);
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nvkm_falcon_del(&gr->fecs);
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gf100_gr_dtor_fw(&gr->fuc409c);
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gf100_gr_dtor_fw(&gr->fuc409d);
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gf100_gr_dtor_fw(&gr->fuc41ac);
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@ -1773,6 +1765,7 @@ gf100_gr_ = {
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.dtor = gf100_gr_dtor,
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.oneinit = gf100_gr_oneinit,
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.init = gf100_gr_init_,
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.fini = gf100_gr_fini_,
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.intr = gf100_gr_intr,
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.units = gf100_gr_units,
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.chan_new = gf100_gr_chan_new,
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@ -1846,6 +1839,7 @@ int
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gf100_gr_ctor(const struct gf100_gr_func *func, struct nvkm_device *device,
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int index, struct gf100_gr *gr)
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{
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struct nvkm_subdev *subdev = &gr->base.engine.subdev;
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int ret;
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gr->func = func;
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@ -1858,7 +1852,11 @@ gf100_gr_ctor(const struct gf100_gr_func *func, struct nvkm_device *device,
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if (ret)
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return ret;
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return 0;
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ret = nvkm_falcon_v1_new(subdev, "FECS", 0x409000, &gr->fecs);
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if (ret)
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return ret;
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return nvkm_falcon_v1_new(subdev, "GPCCS", 0x41a000, &gr->gpccs);
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}
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int
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@ -29,6 +29,7 @@
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#include <core/gpuobj.h>
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#include <subdev/ltc.h>
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#include <subdev/mmu.h>
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#include <engine/falcon.h>
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#define GPC_MAX 32
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#define TPC_MAX_PER_GPC 8
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@ -75,6 +76,8 @@ struct gf100_gr {
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const struct gf100_gr_func *func;
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struct nvkm_gr base;
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struct nvkm_falcon *fecs;
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struct nvkm_falcon *gpccs;
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struct gf100_gr_fuc fuc409c;
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struct gf100_gr_fuc fuc409d;
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struct gf100_gr_fuc fuc41ac;
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