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Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus 

Pull MIPS updates from Ralf Baechle:
 "A fair number of fixes all across arch/mips.  Nothing really stands
  out though APRP, the FPU code and syscall tracing code received
  multiple patches those all were small"

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus:
  MIPS: mark O32+FP64 experimental for now
  MIPS: ftrace: Fix icache flush range error
  MIPS: Fix syscall tracing interface
  MIPS: asm: syscall: Fix copying system call arguments
  MIPS: Octeon: Fix fall through on bar type OCTEON_DMA_BAR_TYPE_SMALL
  MIPS: FPU: Fix conflict of register usage
  MIPS: Replace CONFIG_MIPS64 and CONFIG_MIPS32_R2
  MIPS: math-emu: Fix prefx detection and COP1X function field definition
  MIPS: APRP: Choose the correct VPE loader by fixing the linking
  MIPS: APRP: Unregister rtlx interrupt hook at module exit
  MIPS: APRP: Fix the linking of rtlx interrupt hook
  MIPS: bcm47xx: Include missing errno.h for ENXIO
  MIPS: Alchemy: Fix unchecked kstrtoul return value
  MIPS: Fix randconfig build error.
This commit is contained in:
Linus Torvalds 2014-03-17 16:53:18 -07:00
parent 9f8b483cf3 06e2e88292
commit 8a21d9f63d
16 changed files with 46 additions and 35 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
arch/mips/Kconfig
View File

@ -2353,9 +2353,8 @@ config SECCOMP
If unsure, say Y. Only embedded should say N here.
config MIPS_O32_FP64_SUPPORT
bool "Support for O32 binaries using 64-bit FP"
bool "Support for O32 binaries using 64-bit FP (EXPERIMENTAL)"
depends on 32BIT || MIPS32_O32
default y
help
When this is enabled, the kernel will support use of 64-bit floating
point registers with binaries using the O32 ABI along with the
@ -2367,7 +2366,14 @@ config MIPS_O32_FP64_SUPPORT
of your kernel & potentially improve FP emulation performance by
saying N here.
If unsure, say Y.
Although binutils currently supports use of this flag the details
concerning its effect upon the O32 ABI in userland are still being
worked on. In order to avoid userland becoming dependant upon current
behaviour before the details have been finalised, this option should
be considered experimental and only enabled by those working upon
said details.
If unsure, say N.
config USE_OF
bool

4
arch/mips/alchemy/board-gpr.c
View File

@ -53,10 +53,8 @@ void __init prom_init(void)
prom_init_cmdline();
memsize_str = prom_getenv("memsize");
if (!memsize_str)
if (!memsize_str || kstrtoul(memsize_str, 0, &memsize))
memsize = 0x04000000;
else
strict_strtoul(memsize_str, 0, &memsize);
add_memory_region(0, memsize, BOOT_MEM_RAM);
}

4
arch/mips/alchemy/board-mtx1.c
View File

@ -52,10 +52,8 @@ void __init prom_init(void)
prom_init_cmdline();
memsize_str = prom_getenv("memsize");
if (!memsize_str)
if (!memsize_str || kstrtoul(memsize_str, 0, &memsize))
memsize = 0x04000000;
else
strict_strtoul(memsize_str, 0, &memsize);
add_memory_region(0, memsize, BOOT_MEM_RAM);
}

1
arch/mips/bcm47xx/board.c
View File

@ -1,3 +1,4 @@
#include <linux/errno.h>
#include <linux/export.h>
#include <linux/string.h>
#include <bcm47xx_board.h>

4
arch/mips/include/asm/asmmacro.h
View File

@ -106,7 +106,7 @@
.endm
.macro fpu_save_double thread status tmp
#if defined(CONFIG_MIPS64) || defined(CONFIG_CPU_MIPS32_R2)
#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)
sll \tmp, \status, 5
bgez \tmp, 10f
fpu_save_16odd \thread
@ -159,7 +159,7 @@
.endm
.macro fpu_restore_double thread status tmp
#if defined(CONFIG_MIPS64) || defined(CONFIG_CPU_MIPS32_R2)
#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)
sll \tmp, \status, 5
bgez \tmp, 10f # 16 register mode?

2
arch/mips/include/asm/fpu.h
View File

@ -57,7 +57,7 @@ static inline int __enable_fpu(enum fpu_mode mode)
return 0;
case FPU_64BIT:
#if !(defined(CONFIG_CPU_MIPS32_R2) || defined(CONFIG_MIPS64))
#if !(defined(CONFIG_CPU_MIPS32_R2) || defined(CONFIG_64BIT))
/* we only have a 32-bit FPU */
return SIGFPE;
#endif

10
arch/mips/include/asm/syscall.h
View File

@ -13,6 +13,7 @@
#ifndef __ASM_MIPS_SYSCALL_H
#define __ASM_MIPS_SYSCALL_H
#include <linux/compiler.h>
#include <linux/audit.h>
#include <linux/elf-em.h>
#include <linux/kernel.h>
@ -39,14 +40,14 @@ static inline unsigned long mips_get_syscall_arg(unsigned long *arg,
#ifdef CONFIG_32BIT
case 4: case 5: case 6: case 7:
return get_user(*arg, (int *)usp + 4 * n);
return get_user(*arg, (int *)usp + n);
#endif
#ifdef CONFIG_64BIT
case 4: case 5: case 6: case 7:
#ifdef CONFIG_MIPS32_O32
if (test_thread_flag(TIF_32BIT_REGS))
return get_user(*arg, (int *)usp + 4 * n);
return get_user(*arg, (int *)usp + n);
else
#endif
*arg = regs->regs[4 + n];
@ -57,6 +58,8 @@ static inline unsigned long mips_get_syscall_arg(unsigned long *arg,
default:
BUG();
}
unreachable();
}
static inline long syscall_get_return_value(struct task_struct *task,
@ -83,11 +86,10 @@ static inline void syscall_get_arguments(struct task_struct *task,
unsigned int i, unsigned int n,
unsigned long *args)
{
unsigned long arg;
int ret;
while (n--)
ret |= mips_get_syscall_arg(&arg, task, regs, i++);
ret |= mips_get_syscall_arg(args++, task, regs, i++);
/*
* No way to communicate an error because this is a void function.

4
arch/mips/include/uapi/asm/inst.h
View File

@ -163,8 +163,8 @@ enum cop1_sdw_func {
*/
enum cop1x_func {
lwxc1_op = 0x00, ldxc1_op = 0x01,
pfetch_op = 0x07, swxc1_op = 0x08,
sdxc1_op = 0x09, madd_s_op = 0x20,
swxc1_op = 0x08, sdxc1_op = 0x09,
pfetch_op = 0x0f, madd_s_op = 0x20,
madd_d_op = 0x21, madd_e_op = 0x22,
msub_s_op = 0x28, msub_d_op = 0x29,
msub_e_op = 0x2a, nmadd_s_op = 0x30,

5
arch/mips/kernel/ftrace.c
View File

@ -111,11 +111,10 @@ static int ftrace_modify_code_2(unsigned long ip, unsigned int new_code1,
safe_store_code(new_code1, ip, faulted);
if (unlikely(faulted))
return -EFAULT;
ip += 4;
safe_store_code(new_code2, ip, faulted);
safe_store_code(new_code2, ip + 4, faulted);
if (unlikely(faulted))
return -EFAULT;
flush_icache_range(ip, ip + 8); /* original ip + 12 */
flush_icache_range(ip, ip + 8);
return 0;
}
#endif

16
arch/mips/kernel/r4k_fpu.S
View File

@ -35,9 +35,9 @@
LEAF(_save_fp_context)
cfc1 t1, fcr31
#if defined(CONFIG_64BIT) || defined(CONFIG_MIPS32_R2)
#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)
.set push
#ifdef CONFIG_MIPS32_R2
#ifdef CONFIG_CPU_MIPS32_R2
.set mips64r2
mfc0 t0, CP0_STATUS
sll t0, t0, 5
@ -146,11 +146,11 @@ LEAF(_save_fp_context32)
* - cp1 status/control register
*/
LEAF(_restore_fp_context)
EX lw t0, SC_FPC_CSR(a0)
EX lw t1, SC_FPC_CSR(a0)
#if defined(CONFIG_64BIT) || defined(CONFIG_MIPS32_R2)
#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)
.set push
#ifdef CONFIG_MIPS32_R2
#ifdef CONFIG_CPU_MIPS32_R2
.set mips64r2
mfc0 t0, CP0_STATUS
sll t0, t0, 5
@ -191,7 +191,7 @@ LEAF(_restore_fp_context)
EX ldc1 $f26, SC_FPREGS+208(a0)
EX ldc1 $f28, SC_FPREGS+224(a0)
EX ldc1 $f30, SC_FPREGS+240(a0)
ctc1 t0, fcr31
ctc1 t1, fcr31
jr ra
li v0, 0 # success
END(_restore_fp_context)
@ -199,7 +199,7 @@ LEAF(_restore_fp_context)
#ifdef CONFIG_MIPS32_COMPAT
LEAF(_restore_fp_context32)
/* Restore an o32 sigcontext. */
EX lw t0, SC32_FPC_CSR(a0)
EX lw t1, SC32_FPC_CSR(a0)
mfc0 t0, CP0_STATUS
sll t0, t0, 5
@ -239,7 +239,7 @@ LEAF(_restore_fp_context32)
EX ldc1 $f26, SC32_FPREGS+208(a0)
EX ldc1 $f28, SC32_FPREGS+224(a0)
EX ldc1 $f30, SC32_FPREGS+240(a0)
ctc1 t0, fcr31
ctc1 t1, fcr31
jr ra
li v0, 0 # success
END(_restore_fp_context32)

3
arch/mips/kernel/rtlx-cmp.c
View File

@ -112,5 +112,8 @@ void __exit rtlx_module_exit(void)
for (i = 0; i < RTLX_CHANNELS; i++)
device_destroy(mt_class, MKDEV(major, i));
unregister_chrdev(major, RTLX_MODULE_NAME);
aprp_hook = NULL;
}

3
arch/mips/kernel/rtlx-mt.c
View File

@ -144,5 +144,8 @@ void __exit rtlx_module_exit(void)
for (i = 0; i < RTLX_CHANNELS; i++)
device_destroy(mt_class, MKDEV(major, i));
unregister_chrdev(major, RTLX_MODULE_NAME);
aprp_hook = NULL;
}

6
arch/mips/math-emu/cp1emu.c
View File

@ -1538,10 +1538,10 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
break;
}
case 0x7: /* 7 */
if (MIPSInst_FUNC(ir) != pfetch_op) {
case 0x3:
if (MIPSInst_FUNC(ir) != pfetch_op)
return SIGILL;
}
/* ignore prefx operation */
break;

2
arch/mips/mti-malta/malta-amon.c
View File

@ -72,7 +72,7 @@ int amon_cpu_start(int cpu,
return 0;
}
#ifdef CONFIG_MIPS_VPE_LOADER
#ifdef CONFIG_MIPS_VPE_LOADER_CMP
int vpe_run(struct vpe *v)
{
struct vpe_notifications *n;

4
arch/mips/mti-malta/malta-int.c
View File

@ -119,7 +119,7 @@ static void malta_hw0_irqdispatch(void)
do_IRQ(MALTA_INT_BASE + irq);
#ifdef MIPS_VPE_APSP_API
#ifdef CONFIG_MIPS_VPE_APSP_API_MT
if (aprp_hook)
aprp_hook();
#endif
@ -310,7 +310,7 @@ static void ipi_call_dispatch(void)
static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
{
#ifdef MIPS_VPE_APSP_API
#ifdef CONFIG_MIPS_VPE_APSP_API_CMP
if (aprp_hook)
aprp_hook();
#endif

1
arch/mips/pci/msi-octeon.c
View File

@ -150,6 +150,7 @@ int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
msg.address_lo =
((128ul << 20) + CVMX_PCI_MSI_RCV) & 0xffffffff;
msg.address_hi = ((128ul << 20) + CVMX_PCI_MSI_RCV) >> 32;
break;
case OCTEON_DMA_BAR_TYPE_BIG:
/* When using big bar, Bar 0 is based at 0 */
msg.address_lo = (0 + CVMX_PCI_MSI_RCV) & 0xffffffff;