A set of pin control fixes for the v3.14 series:
- Fix chained interrupts, interrupt masking and register offset
calculation for the sunxi driver.
- Make MSM a bool rather than a tristate to stop build problems
to happen - chained interrupt controllers cannot currently be
defined in modules.
- Fix a clock in the PFC driver.
- Fix a kernel panic in the sirf driver.
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Merge tag 'pinctrl-v3.14-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control fixes from Linus Walleij:
"This is a set of pin control fixes I have collected over the last few
days. Some have rotated more than others in linux-next, but they were
rebased on v3.14-rc5 due to sloppy commit messages. I am quite
convinced that they are all good fixes that only hit this or that
individual driver and not the entire subsystem.
- Fix chained interrupts, interrupt masking and register offset
calculation for the sunxi driver
- Make MSM a bool rather than a tristate to stop build problems to
happen - chained interrupt controllers cannot currently be defined
in modules
- Fix a clock in the PFC driver
- Fix a kernel panic in the sirf driver"
* tag 'pinctrl-v3.14-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
pinctrl: sirf: fix kernel panic in gpio_lock_as_irq
pinctrl: sh-pfc: r8a7791: SD1_CLK fix
pinctrl: msm: make PINCTRL_MSM bool instead of tristate
pinctrl: sunxi: Fix interrupt register offset calculation
pinctrl: sunxi: Fix masking when setting irq type
pinctrl: sunxi: use chained_irq_{enter, exit} for GIC compatibility
This commit is contained in:
Linus Torvalds
commit
8ab47d3ec7
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@ -217,7 +217,7 @@ config PINCTRL_IMX28
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select PINCTRL_MXS
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config PINCTRL_MSM
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tristate
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bool
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select PINMUX
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select PINCONF
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select GENERIC_PINCONF
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@ -14,6 +14,7 @@
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#include <linux/clk.h>
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#include <linux/gpio.h>
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#include <linux/irqdomain.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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@ -584,7 +585,7 @@ static int sunxi_pinctrl_irq_set_type(struct irq_data *d,
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spin_lock_irqsave(&pctl->lock, flags);
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regval = readl(pctl->membase + reg);
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regval &= ~IRQ_CFG_IRQ_MASK;
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regval &= ~(IRQ_CFG_IRQ_MASK << index);
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writel(regval | (mode << index), pctl->membase + reg);
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spin_unlock_irqrestore(&pctl->lock, flags);
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@ -665,6 +666,7 @@ static struct irq_chip sunxi_pinctrl_irq_chip = {
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static void sunxi_pinctrl_irq_handler(unsigned irq, struct irq_desc *desc)
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{
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struct irq_chip *chip = irq_get_chip(irq);
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struct sunxi_pinctrl *pctl = irq_get_handler_data(irq);
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const unsigned long reg = readl(pctl->membase + IRQ_STATUS_REG);
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@ -674,10 +676,12 @@ static void sunxi_pinctrl_irq_handler(unsigned irq, struct irq_desc *desc)
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if (reg) {
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int irqoffset;
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chained_irq_enter(chip, desc);
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for_each_set_bit(irqoffset, ®, SUNXI_IRQ_NUMBER) {
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int pin_irq = irq_find_mapping(pctl->domain, irqoffset);
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generic_handle_irq(pin_irq);
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}
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chained_irq_exit(chip, desc);
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}
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}
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@ -511,7 +511,7 @@ static inline u32 sunxi_pull_offset(u16 pin)
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static inline u32 sunxi_irq_cfg_reg(u16 irq)
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{
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u8 reg = irq / IRQ_CFG_IRQ_PER_REG;
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u8 reg = irq / IRQ_CFG_IRQ_PER_REG * 0x04;
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return reg + IRQ_CFG_REG;
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}
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@ -523,7 +523,7 @@ static inline u32 sunxi_irq_cfg_offset(u16 irq)
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static inline u32 sunxi_irq_ctrl_reg(u16 irq)
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{
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u8 reg = irq / IRQ_CTRL_IRQ_PER_REG;
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u8 reg = irq / IRQ_CTRL_IRQ_PER_REG * 0x04;
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return reg + IRQ_CTRL_REG;
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}
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@ -535,7 +535,7 @@ static inline u32 sunxi_irq_ctrl_offset(u16 irq)
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static inline u32 sunxi_irq_status_reg(u16 irq)
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{
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u8 reg = irq / IRQ_STATUS_IRQ_PER_REG;
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u8 reg = irq / IRQ_STATUS_IRQ_PER_REG * 0x04;
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return reg + IRQ_STATUS_REG;
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}
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@ -89,7 +89,8 @@ enum {
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/* GPSR6 */
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FN_IP13_10, FN_IP13_11, FN_IP13_12, FN_IP13_13, FN_IP13_14,
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FN_IP13_15, FN_IP13_18_16, FN_IP13_21_19, FN_IP13_22, FN_IP13_24_23,
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FN_IP13_15, FN_IP13_18_16, FN_IP13_21_19,
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FN_IP13_22, FN_IP13_24_23, FN_SD1_CLK,
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FN_IP13_25, FN_IP13_26, FN_IP13_27, FN_IP13_30_28, FN_IP14_1_0,
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FN_IP14_2, FN_IP14_3, FN_IP14_4, FN_IP14_5, FN_IP14_6, FN_IP14_7,
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FN_IP14_10_8, FN_IP14_13_11, FN_IP14_16_14, FN_IP14_19_17,
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@ -788,6 +789,7 @@ static const u16 pinmux_data[] = {
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PINMUX_DATA(USB1_PWEN_MARK, FN_USB1_PWEN),
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PINMUX_DATA(USB1_OVC_MARK, FN_USB1_OVC),
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PINMUX_DATA(DU0_DOTCLKIN_MARK, FN_DU0_DOTCLKIN),
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PINMUX_DATA(SD1_CLK_MARK, FN_SD1_CLK),
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/* IPSR0 */
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PINMUX_IPSR_DATA(IP0_0, D0),
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@ -3825,7 +3827,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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GP_6_11_FN, FN_IP13_25,
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GP_6_10_FN, FN_IP13_24_23,
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GP_6_9_FN, FN_IP13_22,
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0, 0,
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GP_6_8_FN, FN_SD1_CLK,
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GP_6_7_FN, FN_IP13_21_19,
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GP_6_6_FN, FN_IP13_18_16,
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GP_6_5_FN, FN_IP13_15,
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@ -598,7 +598,7 @@ static unsigned int sirfsoc_gpio_irq_startup(struct irq_data *d)
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{
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struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d);
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if (gpio_lock_as_irq(&bank->chip.gc, d->hwirq))
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if (gpio_lock_as_irq(&bank->chip.gc, d->hwirq % SIRFSOC_GPIO_BANK_SIZE))
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dev_err(bank->chip.gc.dev,
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"unable to lock HW IRQ %lu for IRQ\n",
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d->hwirq);
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@ -611,7 +611,7 @@ static void sirfsoc_gpio_irq_shutdown(struct irq_data *d)
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struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d);
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sirfsoc_gpio_irq_mask(d);
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gpio_unlock_as_irq(&bank->chip.gc, d->hwirq);
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gpio_unlock_as_irq(&bank->chip.gc, d->hwirq % SIRFSOC_GPIO_BANK_SIZE);
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}
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static struct irq_chip sirfsoc_irq_chip = {
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