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s390: rename psw_bits enums 

The address space enums that must be used when modifying the address
space part of a psw with the psw_bits() macro can easily be confused
with the psw defines that are used to mask and compare directly the
mask part of a psw.
We have e.g. PSW_AS_PRIMARY vs PSW_ASC_PRIMARY.

To avoid confusion rename the PSW_AS_* enums to PSW_BITS_AS_*.

In addition also rename the PSW_AMODE_* enums, so they also follow the
same naming scheme: PSW_BITS_AMODE_*.

Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
This commit is contained in:
Heiko Carstens 2017-06-03 10:19:55 +02:00 committed by Martin Schwidefsky
parent 60c497014e
commit 8bb3fdd686
7 changed files with 26 additions and 26 deletions
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14
arch/s390/include/asm/ptrace.h
View File

@ -46,16 +46,16 @@ struct psw_bits {
}; };
enum { enum {
PSW_AMODE_24BIT = 0, PSW_BITS_AMODE_24BIT = 0,
PSW_AMODE_31BIT = 1, PSW_BITS_AMODE_31BIT = 1,
PSW_AMODE_64BIT = 3 PSW_BITS_AMODE_64BIT = 3
}; };
enum { enum {
PSW_AS_PRIMARY = 0, PSW_BITS_AS_PRIMARY = 0,
PSW_AS_ACCREG = 1, PSW_BITS_AS_ACCREG = 1,
PSW_AS_SECONDARY = 2, PSW_BITS_AS_SECONDARY = 2,
PSW_AS_HOME = 3 PSW_BITS_AS_HOME = 3
}; };
#define psw_bits(__psw) (*({ \ #define psw_bits(__psw) (*({ \

8
arch/s390/kernel/uprobes.c
View File

@ -27,9 +27,9 @@ int arch_uprobe_analyze_insn(struct arch_uprobe *auprobe, struct mm_struct *mm,
int arch_uprobe_pre_xol(struct arch_uprobe *auprobe, struct pt_regs *regs) int arch_uprobe_pre_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
{ {
if (psw_bits(regs->psw).eaba == PSW_AMODE_24BIT) if (psw_bits(regs->psw).eaba == PSW_BITS_AMODE_24BIT)
return -EINVAL; return -EINVAL;
if (!is_compat_task() && psw_bits(regs->psw).eaba == PSW_AMODE_31BIT) if (!is_compat_task() && psw_bits(regs->psw).eaba == PSW_BITS_AMODE_31BIT)
return -EINVAL; return -EINVAL;
clear_pt_regs_flag(regs, PIF_PER_TRAP); clear_pt_regs_flag(regs, PIF_PER_TRAP);
auprobe->saved_per = psw_bits(regs->psw).r; auprobe->saved_per = psw_bits(regs->psw).r;
@ -372,8 +372,8 @@ static void handle_insn_ril(struct arch_uprobe *auprobe, struct pt_regs *regs)
bool arch_uprobe_skip_sstep(struct arch_uprobe *auprobe, struct pt_regs *regs) bool arch_uprobe_skip_sstep(struct arch_uprobe *auprobe, struct pt_regs *regs)
{ {
if ((psw_bits(regs->psw).eaba == PSW_AMODE_24BIT) || if ((psw_bits(regs->psw).eaba == PSW_BITS_AMODE_24BIT) ||
((psw_bits(regs->psw).eaba == PSW_AMODE_31BIT) && ((psw_bits(regs->psw).eaba == PSW_BITS_AMODE_31BIT) &&
!is_compat_task())) { !is_compat_task())) {
regs->psw.addr = __rewind_psw(regs->psw, UPROBE_SWBP_INSN_SIZE); regs->psw.addr = __rewind_psw(regs->psw, UPROBE_SWBP_INSN_SIZE);
do_report_trap(regs, SIGILL, ILL_ILLADR, NULL); do_report_trap(regs, SIGILL, ILL_ILLADR, NULL);

12
arch/s390/kvm/gaccess.c
View File

@ -557,20 +557,20 @@ static int get_vcpu_asce(struct kvm_vcpu *vcpu, union asce *asce,
return 0; return 0;
} }
if (mode == GACC_IFETCH) if ((mode == GACC_IFETCH) && (psw.as != PSW_BITS_AS_HOME))
psw.as = psw.as == PSW_AS_HOME ? PSW_AS_HOME : PSW_AS_PRIMARY; psw.as = PSW_BITS_AS_PRIMARY;
switch (psw.as) { switch (psw.as) {
case PSW_AS_PRIMARY: case PSW_BITS_AS_PRIMARY:
asce->val = vcpu->arch.sie_block->gcr[1]; asce->val = vcpu->arch.sie_block->gcr[1];
return 0; return 0;
case PSW_AS_SECONDARY: case PSW_BITS_AS_SECONDARY:
asce->val = vcpu->arch.sie_block->gcr[7]; asce->val = vcpu->arch.sie_block->gcr[7];
return 0; return 0;
case PSW_AS_HOME: case PSW_BITS_AS_HOME:
asce->val = vcpu->arch.sie_block->gcr[13]; asce->val = vcpu->arch.sie_block->gcr[13];
return 0; return 0;
case PSW_AS_ACCREG: case PSW_BITS_AS_ACCREG:
rc = ar_translation(vcpu, asce, ar, mode); rc = ar_translation(vcpu, asce, ar, mode);
if (rc > 0) if (rc > 0)
return trans_exc(vcpu, rc, ga, ar, mode, PROT_TYPE_ALC); return trans_exc(vcpu, rc, ga, ar, mode, PROT_TYPE_ALC);

4
arch/s390/kvm/gaccess.h
View File

@ -57,9 +57,9 @@ static inline unsigned long kvm_s390_logical_to_effective(struct kvm_vcpu *vcpu,
{ {
psw_t *psw = &vcpu->arch.sie_block->gpsw; psw_t *psw = &vcpu->arch.sie_block->gpsw;
if (psw_bits(*psw).eaba == PSW_AMODE_64BIT) if (psw_bits(*psw).eaba == PSW_BITS_AMODE_64BIT)
return ga; return ga;
if (psw_bits(*psw).eaba == PSW_AMODE_31BIT) if (psw_bits(*psw).eaba == PSW_BITS_AMODE_31BIT)
return ga & ((1UL << 31) - 1); return ga & ((1UL << 31) - 1);
return ga & ((1UL << 24) - 1); return ga & ((1UL << 24) - 1);
} }

6
arch/s390/kvm/guestdbg.c
View File

@ -613,15 +613,15 @@ int kvm_s390_handle_per_event(struct kvm_vcpu *vcpu)
* instruction. Check primary and home space-switch-event * instruction. Check primary and home space-switch-event
* controls. (theoretically home -> home produced no event) * controls. (theoretically home -> home produced no event)
*/ */
if (((new_as == PSW_AS_HOME) ^ old_as_is_home(vcpu)) && if (((new_as == PSW_BITS_AS_HOME) ^ old_as_is_home(vcpu)) &&
(pssec(vcpu) || hssec(vcpu))) (pssec(vcpu) || hssec(vcpu)))
vcpu->arch.sie_block->iprcc = PGM_SPACE_SWITCH; vcpu->arch.sie_block->iprcc = PGM_SPACE_SWITCH;
/* /*
* PT, PTI, PR, PC instruction operate on primary AS only. Check * PT, PTI, PR, PC instruction operate on primary AS only. Check
* if the primary-space-switch-event control was or got set. * if the primary-space-switch-event control was or got set.
*/ */
if (new_as == PSW_AS_PRIMARY && !old_as_is_home(vcpu) && if (new_as == PSW_BITS_AS_PRIMARY && !old_as_is_home(vcpu) &&
(pssec(vcpu) || old_ssec(vcpu))) (pssec(vcpu) || old_ssec(vcpu)))
vcpu->arch.sie_block->iprcc = PGM_SPACE_SWITCH; vcpu->arch.sie_block->iprcc = PGM_SPACE_SWITCH;
} }

6
arch/s390/kvm/priv.c
View File

@ -361,7 +361,7 @@ static int handle_sske(struct kvm_vcpu *vcpu)
} }
} }
if (m3 & SSKE_MB) { if (m3 & SSKE_MB) {
if (psw_bits(vcpu->arch.sie_block->gpsw).eaba == PSW_AMODE_64BIT) if (psw_bits(vcpu->arch.sie_block->gpsw).eaba == PSW_BITS_AMODE_64BIT)
vcpu->run->s.regs.gprs[reg2] &= ~PAGE_MASK; vcpu->run->s.regs.gprs[reg2] &= ~PAGE_MASK;
else else
vcpu->run->s.regs.gprs[reg2] &= ~0xfffff000UL; vcpu->run->s.regs.gprs[reg2] &= ~0xfffff000UL;
@ -901,7 +901,7 @@ static int handle_pfmf(struct kvm_vcpu *vcpu)
/* only support 2G frame size if EDAT2 is available and we are /* only support 2G frame size if EDAT2 is available and we are
not in 24-bit addressing mode */ not in 24-bit addressing mode */
if (!test_kvm_facility(vcpu->kvm, 78) || if (!test_kvm_facility(vcpu->kvm, 78) ||
psw_bits(vcpu->arch.sie_block->gpsw).eaba == PSW_AMODE_24BIT) psw_bits(vcpu->arch.sie_block->gpsw).eaba == PSW_BITS_AMODE_24BIT)
return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION); return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION);
end = (start + (1UL << 31)) & ~((1UL << 31) - 1); end = (start + (1UL << 31)) & ~((1UL << 31) - 1);
break; break;
@ -938,7 +938,7 @@ static int handle_pfmf(struct kvm_vcpu *vcpu)
start += PAGE_SIZE; start += PAGE_SIZE;
} }
if (vcpu->run->s.regs.gprs[reg1] & PFMF_FSC) { if (vcpu->run->s.regs.gprs[reg1] & PFMF_FSC) {
if (psw_bits(vcpu->arch.sie_block->gpsw).eaba == PSW_AMODE_64BIT) { if (psw_bits(vcpu->arch.sie_block->gpsw).eaba == PSW_BITS_AMODE_64BIT) {
vcpu->run->s.regs.gprs[reg2] = end; vcpu->run->s.regs.gprs[reg2] = end;
} else { } else {
vcpu->run->s.regs.gprs[reg2] &= ~0xffffffffUL; vcpu->run->s.regs.gprs[reg2] &= ~0xffffffffUL;

2
arch/s390/mm/init.c
View File

@ -103,7 +103,7 @@ void __init paging_init(void)
__ctl_load(S390_lowcore.kernel_asce, 13, 13); __ctl_load(S390_lowcore.kernel_asce, 13, 13);
psw.mask = __extract_psw(); psw.mask = __extract_psw();
psw_bits(psw).t = 1; psw_bits(psw).t = 1;
psw_bits(psw).as = PSW_AS_HOME; psw_bits(psw).as = PSW_BITS_AS_HOME;
__load_psw_mask(psw.mask); __load_psw_mask(psw.mask);
sparse_memory_present_with_active_regions(MAX_NUMNODES); sparse_memory_present_with_active_regions(MAX_NUMNODES);