p71924506
/
linux_old1
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

dt-bindings: medaitek: mt8183: add property "resets" && "reset-names" 

This patch add property "resets" && "reset-names" in examples so that we can
use reset controller to reset audio domain regs.

Signed-off-by: Jiaxin Yu <jiaxin.yu@mediatek.com>
Link: https://lore.kernel.org/r/1569580317-21181-4-git-send-email-jiaxin.yu@mediatek.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Jiaxin Yu 2019-09-27 18:31:56 +08:00 committed by Mark Brown
parent cfc28ac124
commit 8d6aa1367a
No known key found for this signature in database
GPG Key ID: 24D68B725D5487D0
1 changed files with 6 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
Documentation/devicetree/bindings/sound/mt8183-afe-pcm.txt
View File

@ -4,6 +4,10 @@ Required properties:
- compatible = "mediatek,mt68183-audio"; - compatible = "mediatek,mt68183-audio";
- reg: register location and size - reg: register location and size
- interrupts: should contain AFE interrupt - interrupts: should contain AFE interrupt
- resets: Must contain an entry for each entry in reset-names
See ../reset/reset.txt for details.
- reset-names: should have these reset names:
"audiosys";
- power-domains: should define the power domain - power-domains: should define the power domain
- clocks: Must contain an entry for each entry in clock-names - clocks: Must contain an entry for each entry in clock-names
- clock-names: should have these clock names: - clock-names: should have these clock names:
@ -20,6 +24,8 @@ Example:
compatible = "mediatek,mt8183-audio"; compatible = "mediatek,mt8183-audio";
reg = <0 0x11220000 0 0x1000>; reg = <0 0x11220000 0 0x1000>;
interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>; interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>;
resets = <&watchdog MT8183_TOPRGU_AUDIO_SW_RST>;
reset-names = "audiosys";
power-domains = <&scpsys MT8183_POWER_DOMAIN_AUDIO>; power-domains = <&scpsys MT8183_POWER_DOMAIN_AUDIO>;
clocks = <&infrasys CLK_INFRA_AUDIO>, clocks = <&infrasys CLK_INFRA_AUDIO>,
<&infrasys CLK_INFRA_AUDIO_26M_BCLK>, <&infrasys CLK_INFRA_AUDIO_26M_BCLK>,