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clk: tegra: Don't warn for PLL defaults unnecessarily 

If the PLL is on, only warn if the defaults are not yet set. Otherwise
be silent.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Tested-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Peter De Schrijver 2017-02-23 12:44:42 +02:00 committed by Thierry Reding
parent 8809eeac21
commit 8dce89a1c2
1 changed files with 12 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
drivers/clk/tegra/clk-tegra210.c
View File

@ -502,7 +502,7 @@ static void tegra210_pllcx_set_defaults(const char *name,
pllcx->params->defaults_set = true; pllcx->params->defaults_set = true;
if (readl_relaxed(clk_base + pllcx->params->base_reg) & if (readl_relaxed(clk_base + pllcx->params->base_reg) &
PLL_ENABLE) { PLL_ENABLE && !pllcx->params->defaults_set) {
/* PLL is ON: only check if defaults already set */ /* PLL is ON: only check if defaults already set */
pllcx_check_defaults(pllcx->params); pllcx_check_defaults(pllcx->params);
pr_warn("%s already enabled. Postponing set full defaults\n", pr_warn("%s already enabled. Postponing set full defaults\n",
@ -608,7 +608,6 @@ static void tegra210_plld_set_defaults(struct tegra_clk_pll *plld)
if (readl_relaxed(clk_base + plld->params->base_reg) & if (readl_relaxed(clk_base + plld->params->base_reg) &
PLL_ENABLE) { PLL_ENABLE) {
pr_warn("PLL_D already enabled. Postponing set full defaults\n");
/* /*
* PLL is ON: check if defaults already set, then set those * PLL is ON: check if defaults already set, then set those
@ -625,6 +624,9 @@ static void tegra210_plld_set_defaults(struct tegra_clk_pll *plld)
_pll_misc_chk_default(clk_base, plld->params, 0, val, _pll_misc_chk_default(clk_base, plld->params, 0, val,
~mask & PLLD_MISC0_WRITE_MASK); ~mask & PLLD_MISC0_WRITE_MASK);
if (!plld->params->defaults_set)
pr_warn("PLL_D already enabled. Postponing set full defaults\n");
/* Enable lock detect */ /* Enable lock detect */
mask = PLLD_MISC0_LOCK_ENABLE | PLLD_MISC0_LOCK_OVERRIDE; mask = PLLD_MISC0_LOCK_ENABLE | PLLD_MISC0_LOCK_OVERRIDE;
val = readl_relaxed(clk_base + plld->params->ext_misc_reg[0]); val = readl_relaxed(clk_base + plld->params->ext_misc_reg[0]);
@ -896,7 +898,6 @@ static void tegra210_pllx_set_defaults(struct tegra_clk_pll *pllx)
val |= step_b << PLLX_MISC2_DYNRAMP_STEPB_SHIFT; val |= step_b << PLLX_MISC2_DYNRAMP_STEPB_SHIFT;
if (readl_relaxed(clk_base + pllx->params->base_reg) & PLL_ENABLE) { if (readl_relaxed(clk_base + pllx->params->base_reg) & PLL_ENABLE) {
pr_warn("PLL_X already enabled. Postponing set full defaults\n");
/* /*
* PLL is ON: check if defaults already set, then set those * PLL is ON: check if defaults already set, then set those
@ -904,6 +905,8 @@ static void tegra210_pllx_set_defaults(struct tegra_clk_pll *pllx)
*/ */
pllx_check_defaults(pllx); pllx_check_defaults(pllx);
if (!pllx->params->defaults_set)
pr_warn("PLL_X already enabled. Postponing set full defaults\n");
/* Configure dyn ramp, disable lock override */ /* Configure dyn ramp, disable lock override */
writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]); writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
@ -948,7 +951,6 @@ static void tegra210_pllmb_set_defaults(struct tegra_clk_pll *pllmb)
pllmb->params->defaults_set = true; pllmb->params->defaults_set = true;
if (val & PLL_ENABLE) { if (val & PLL_ENABLE) {
pr_warn("PLL_MB already enabled. Postponing set full defaults\n");
/* /*
* PLL is ON: check if defaults already set, then set those * PLL is ON: check if defaults already set, then set those
@ -959,6 +961,8 @@ static void tegra210_pllmb_set_defaults(struct tegra_clk_pll *pllmb)
_pll_misc_chk_default(clk_base, pllmb->params, 0, val, _pll_misc_chk_default(clk_base, pllmb->params, 0, val,
~mask & PLLMB_MISC1_WRITE_MASK); ~mask & PLLMB_MISC1_WRITE_MASK);
if (!pllmb->params->defaults_set)
pr_warn("PLL_MB already enabled. Postponing set full defaults\n");
/* Enable lock detect */ /* Enable lock detect */
val = readl_relaxed(clk_base + pllmb->params->ext_misc_reg[0]); val = readl_relaxed(clk_base + pllmb->params->ext_misc_reg[0]);
val &= ~mask; val &= ~mask;
@ -1008,13 +1012,14 @@ static void tegra210_pllp_set_defaults(struct tegra_clk_pll *pllp)
pllp->params->defaults_set = true; pllp->params->defaults_set = true;
if (val & PLL_ENABLE) { if (val & PLL_ENABLE) {
pr_warn("PLL_P already enabled. Postponing set full defaults\n");
/* /*
* PLL is ON: check if defaults already set, then set those * PLL is ON: check if defaults already set, then set those
* that can be updated in flight. * that can be updated in flight.
*/ */
pllp_check_defaults(pllp, true); pllp_check_defaults(pllp, true);
if (!pllp->params->defaults_set)
pr_warn("PLL_P already enabled. Postponing set full defaults\n");
/* Enable lock detect */ /* Enable lock detect */
val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[0]); val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[0]);
@ -1069,13 +1074,14 @@ static void tegra210_pllu_set_defaults(struct tegra_clk_pll *pllu)
pllu->params->defaults_set = true; pllu->params->defaults_set = true;
if (val & PLL_ENABLE) { if (val & PLL_ENABLE) {
pr_warn("PLL_U already enabled. Postponing set full defaults\n");
/* /*
* PLL is ON: check if defaults already set, then set those * PLL is ON: check if defaults already set, then set those
* that can be updated in flight. * that can be updated in flight.
*/ */
pllu_check_defaults(pllu, false); pllu_check_defaults(pllu, false);
if (!pllu->params->defaults_set)
pr_warn("PLL_U already enabled. Postponing set full defaults\n");
/* Enable lock detect */ /* Enable lock detect */
val = readl_relaxed(clk_base + pllu->params->ext_misc_reg[0]); val = readl_relaxed(clk_base + pllu->params->ext_misc_reg[0]);