ARM: shmobile: r8a7794: Add SDHI clocks to device tree
Signed-off-by: Shinobu Uehara <shinobu.uehara.xc@renesas.com> [horms: omitted device nodes; only add clock] Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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@ -293,6 +293,21 @@ cpg_clocks: cpg_clocks@e6150000 {
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clock-output-names = "main", "pll0", "pll1", "pll3",
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"lb", "qspi", "sdh", "sd0", "z";
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};
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/* Variable factor clocks */
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sd1_clk: sd2_clk@e6150078 {
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compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
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reg = <0 0xe6150078 0 4>;
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clocks = <&pll1_div2_clk>;
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#clock-cells = <0>;
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clock-output-names = "sd1";
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};
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sd2_clk: sd3_clk@e615007c {
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compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
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reg = <0 0xe615007c 0 4>;
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clocks = <&pll1_div2_clk>;
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#clock-cells = <0>;
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clock-output-names = "sd2";
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};
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/* Fixed factor clocks */
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pll1_div2_clk: pll1_div2_clk {
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@ -496,13 +511,16 @@ R8A7794_CLK_SYS_DMAC1 R8A7794_CLK_SYS_DMAC0
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mstp3_clks: mstp3_clks@e615013c {
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compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
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reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
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clocks = <&rclk_clk>, <&hp_clk>, <&hp_clk>;
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clocks = <&sd2_clk>, <&sd1_clk>, <&cpg_clocks R8A7794_CLK_SD0>,
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<&rclk_clk>, <&hp_clk>, <&hp_clk>;
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#clock-cells = <1>;
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clock-indices = <
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R8A7794_CLK_SDHI2 R8A7794_CLK_SDHI1 R8A7794_CLK_SDHI0
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R8A7794_CLK_CMT1 R8A7794_CLK_USBDMAC0
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R8A7794_CLK_USBDMAC1
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>;
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clock-output-names =
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"sdhi2", "sdhi1", "sdhi0",
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"cmt1", "usbdmac0", "usbdmac1";
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};
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mstp7_clks: mstp7_clks@e615014c {
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@ -52,6 +52,9 @@
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#define R8A7794_CLK_SYS_DMAC0 19
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/* MSTP3 */
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#define R8A7794_CLK_SDHI2 11
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#define R8A7794_CLK_SDHI1 12
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#define R8A7794_CLK_SDHI0 14
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#define R8A7794_CLK_CMT1 29
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#define R8A7794_CLK_USBDMAC0 30
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#define R8A7794_CLK_USBDMAC1 31
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