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cxgb4: collect TID info dump 

Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Signed-off-by: Ganesh Goudar <ganeshgr@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Rahul Lakkireddy 2017-10-26 17:18:36 +05:30 committed by David S. Miller
parent 28b445561f
commit 9030e49897
8 changed files with 143 additions and 1 deletions
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39
drivers/net/ethernet/chelsio/cxgb4/cudbg_entity.h
View File

@ -21,6 +21,8 @@
#define EDC0_FLAG 3
#define EDC1_FLAG 4
#define CUDBG_ENTITY_SIGNATURE 0xCCEDB001
struct card_mem {
u16 size_edc0;
u16 size_edc1;
@ -75,6 +77,43 @@ struct cudbg_cim_pif_la {
u8 data[0];
};
struct cudbg_tid_info_region {
u32 ntids;
u32 nstids;
u32 stid_base;
u32 hash_base;
u32 natids;
u32 nftids;
u32 ftid_base;
u32 aftid_base;
u32 aftid_end;
u32 sftid_base;
u32 nsftids;
u32 uotid_base;
u32 nuotids;
u32 sb;
u32 flags;
u32 le_db_conf;
u32 ip_users;
u32 ipv6_users;
u32 hpftid_base;
u32 nhpftids;
};
#define CUDBG_TID_INFO_REV 1
struct cudbg_tid_info_region_rev1 {
struct cudbg_ver_hdr ver_hdr;
struct cudbg_tid_info_region tid;
u32 tid_start;
u32 reserved[16];
};
#define CUDBG_NUM_ULPTX 11
#define CUDBG_NUM_ULPTX_READ 512

1
drivers/net/ethernet/chelsio/cxgb4/cudbg_if.h
View File

@ -57,6 +57,7 @@ enum cudbg_dbg_entity_type {
CUDBG_CIM_OBQ_RXQ1 = 48,
CUDBG_PCIE_INDIRECT = 50,
CUDBG_PM_INDIRECT = 51,
CUDBG_TID_INFO = 54,
CUDBG_MA_INDIRECT = 61,
CUDBG_ULPTX_LA = 62,
CUDBG_UP_CIM_INDIRECT = 64,

85
drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c
View File

@ -902,6 +902,91 @@ int cudbg_collect_pm_indirect(struct cudbg_init *pdbg_init,
return rc;
}
int cudbg_collect_tid(struct cudbg_init *pdbg_init,
struct cudbg_buffer *dbg_buff,
struct cudbg_error *cudbg_err)
{
struct adapter *padap = pdbg_init->adap;
struct cudbg_tid_info_region_rev1 *tid1;
struct cudbg_buffer temp_buff = { 0 };
struct cudbg_tid_info_region *tid;
u32 para[2], val[2];
int rc;
rc = cudbg_get_buff(dbg_buff, sizeof(struct cudbg_tid_info_region_rev1),
&temp_buff);
if (rc)
return rc;
tid1 = (struct cudbg_tid_info_region_rev1 *)temp_buff.data;
tid = &tid1->tid;
tid1->ver_hdr.signature = CUDBG_ENTITY_SIGNATURE;
tid1->ver_hdr.revision = CUDBG_TID_INFO_REV;
tid1->ver_hdr.size = sizeof(struct cudbg_tid_info_region_rev1) -
sizeof(struct cudbg_ver_hdr);
#define FW_PARAM_PFVF_A(param) \
(FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | \
FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_##param) | \
FW_PARAMS_PARAM_Y_V(0) | \
FW_PARAMS_PARAM_Z_V(0))
para[0] = FW_PARAM_PFVF_A(ETHOFLD_START);
para[1] = FW_PARAM_PFVF_A(ETHOFLD_END);
rc = t4_query_params(padap, padap->mbox, padap->pf, 0, 2, para, val);
if (rc < 0) {
cudbg_err->sys_err = rc;
cudbg_put_buff(&temp_buff, dbg_buff);
return rc;
}
tid->uotid_base = val[0];
tid->nuotids = val[1] - val[0] + 1;
if (is_t5(padap->params.chip)) {
tid->sb = t4_read_reg(padap, LE_DB_SERVER_INDEX_A) / 4;
} else if (is_t6(padap->params.chip)) {
tid1->tid_start =
t4_read_reg(padap, LE_DB_ACTIVE_TABLE_START_INDEX_A);
tid->sb = t4_read_reg(padap, LE_DB_SRVR_START_INDEX_A);
para[0] = FW_PARAM_PFVF_A(HPFILTER_START);
para[1] = FW_PARAM_PFVF_A(HPFILTER_END);
rc = t4_query_params(padap, padap->mbox, padap->pf, 0, 2,
para, val);
if (rc < 0) {
cudbg_err->sys_err = rc;
cudbg_put_buff(&temp_buff, dbg_buff);
return rc;
}
tid->hpftid_base = val[0];
tid->nhpftids = val[1] - val[0] + 1;
}
tid->ntids = padap->tids.ntids;
tid->nstids = padap->tids.nstids;
tid->stid_base = padap->tids.stid_base;
tid->hash_base = padap->tids.hash_base;
tid->natids = padap->tids.natids;
tid->nftids = padap->tids.nftids;
tid->ftid_base = padap->tids.ftid_base;
tid->aftid_base = padap->tids.aftid_base;
tid->aftid_end = padap->tids.aftid_end;
tid->sftid_base = padap->tids.sftid_base;
tid->nsftids = padap->tids.nsftids;
tid->flags = padap->flags;
tid->le_db_conf = t4_read_reg(padap, LE_DB_CONFIG_A);
tid->ip_users = t4_read_reg(padap, LE_DB_ACT_CNT_IPV4_A);
tid->ipv6_users = t4_read_reg(padap, LE_DB_ACT_CNT_IPV6_A);
#undef FW_PARAM_PFVF_A
cudbg_write_and_release_buff(&temp_buff, dbg_buff);
return rc;
}
int cudbg_collect_ma_indirect(struct cudbg_init *pdbg_init,
struct cudbg_buffer *dbg_buff,
struct cudbg_error *cudbg_err)

3
drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.h
View File

@ -108,6 +108,9 @@ int cudbg_collect_pcie_indirect(struct cudbg_init *pdbg_init,
int cudbg_collect_pm_indirect(struct cudbg_init *pdbg_init,
struct cudbg_buffer *dbg_buff,
struct cudbg_error *cudbg_err);
int cudbg_collect_tid(struct cudbg_init *pdbg_init,
struct cudbg_buffer *dbg_buff,
struct cudbg_error *cudbg_err);
int cudbg_collect_ma_indirect(struct cudbg_init *pdbg_init,
struct cudbg_buffer *dbg_buff,
struct cudbg_error *cudbg_err);

6
drivers/net/ethernet/chelsio/cxgb4/cudbg_lib_common.h
View File

@ -57,6 +57,12 @@ struct cudbg_entity_hdr {
u32 reserved[5];
};
struct cudbg_ver_hdr {
u32 signature;
u16 revision;
u16 size;
};
struct cudbg_buffer {
u32 size;
u32 offset;

4
drivers/net/ethernet/chelsio/cxgb4/cxgb4_cudbg.c
View File

@ -55,6 +55,7 @@ static const struct cxgb4_collect_entity cxgb4_collect_hw_dump[] = {
{ CUDBG_CIM_OBQ_RXQ1, cudbg_collect_obq_sge_rx_q1 },
{ CUDBG_PCIE_INDIRECT, cudbg_collect_pcie_indirect },
{ CUDBG_PM_INDIRECT, cudbg_collect_pm_indirect },
{ CUDBG_TID_INFO, cudbg_collect_tid },
{ CUDBG_MA_INDIRECT, cudbg_collect_ma_indirect },
{ CUDBG_ULPTX_LA, cudbg_collect_ulptx_la },
{ CUDBG_UP_CIM_INDIRECT, cudbg_collect_up_cim_indirect },
@ -192,6 +193,9 @@ static u32 cxgb4_get_entity_length(struct adapter *adap, u32 entity)
n = sizeof(t5_pm_rx_array) / (IREG_NUM_ELEM * sizeof(u32));
len = sizeof(struct ireg_buf) * n * 2;
break;
case CUDBG_TID_INFO:
len = sizeof(struct cudbg_tid_info_region_rev1);
break;
case CUDBG_MA_INDIRECT:
if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) {
n = sizeof(t6_ma_ireg_array) /

1
drivers/net/ethernet/chelsio/cxgb4/t4_regs.h
View File

@ -2856,6 +2856,7 @@
#define T6_LIPMISS_F T6_LIPMISS_V(1U)
#define LE_DB_CONFIG_A 0x19c04
#define LE_DB_ACTIVE_TABLE_START_INDEX_A 0x19c10
#define LE_DB_SERVER_INDEX_A 0x19c18
#define LE_DB_SRVR_START_INDEX_A 0x19c18
#define LE_DB_ACT_CNT_IPV4_A 0x19c20

5
drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h
View File

@ -1244,9 +1244,12 @@ enum fw_params_param_pfvf {
FW_PARAMS_PARAM_PFVF_EQ_END = 0x2C,
FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D,
FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E,
FW_PARAMS_PARAM_PFVF_ETHOFLD_START = 0x2F,
FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30,
FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31,
FW_PARAMS_PARAM_PFVF_NCRYPTO_LOOKASIDE = 0x32,
FW_PARAMS_PARAM_PFVF_HPFILTER_START = 0x32,
FW_PARAMS_PARAM_PFVF_HPFILTER_END = 0x33,
FW_PARAMS_PARAM_PFVF_NCRYPTO_LOOKASIDE = 0x39,
FW_PARAMS_PARAM_PFVF_PORT_CAPS32 = 0x3A,
};