p71924506
/
linux_old1
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

ARM: dts: zynq: Enable PL clocks for Parallella 

The Parallella board comes with a U-Boot bootloader that loads one of
two predefined FPGA bitstreams before booting the kernel. Both define an
AXI interface to the on-board Epiphany processor.

Enable clocks FCLK0..FCLK3 for the Programmable Logic by default.

Otherwise accessing, e.g., the ESYSRESET register freezes the board,
as seen with the Epiphany SDK tools e-reset and e-hw-rev, using /dev/mem.

Cc: <stable@vger.kernel.org> # 3.17.x
Signed-off-by: Andreas Färber <afaerber@suse.de>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Andreas Färber 2014-11-06 18:22:10 +01:00 committed by Olof Johansson
parent 5305e4d674
commit 92c9e0c780
1 changed files with 4 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm/boot/dts/zynq-parallella.dts
View File

@ -34,6 +34,10 @@ chosen {
}; };
}; };
&clkc {
fclk-enable = <0xf>;
};
&gem0 { &gem0 {
status = "okay"; status = "okay";
phy-mode = "rgmii-id"; phy-mode = "rgmii-id";