MIPS: math-emu: Convert debug printks to pr_debug getting.
And another bunch of #ifdefs bite the dust. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -1119,11 +1119,9 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
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value = ctx->fcr31;
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value = (value & ~FPU_CSR_RM) |
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mips_rm[modeindex(value)];
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#ifdef CSRTRACE
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printk("%p gpr[%d]<-csr=%08x\n",
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(void *) (xcp->cp0_epc),
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MIPSInst_RT(ir), value);
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#endif
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pr_debug("%p gpr[%d]<-csr=%08x\n",
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(void *) (xcp->cp0_epc),
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MIPSInst_RT(ir), value);
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}
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else if (MIPSInst_RD(ir) == FPCREG_RID)
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value = 0;
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@ -1146,11 +1144,9 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
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/* we only have one writable control reg
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*/
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if (MIPSInst_RD(ir) == FPCREG_CSR) {
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#ifdef CSRTRACE
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printk("%p gpr[%d]->csr=%08x\n",
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(void *) (xcp->cp0_epc),
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MIPSInst_RT(ir), value);
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#endif
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pr_debug("%p gpr[%d]->csr=%08x\n",
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(void *) (xcp->cp0_epc),
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MIPSInst_RT(ir), value);
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/*
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* Don't write reserved bits,
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@ -44,10 +44,8 @@ int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc)
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clear_delay_slot(regs);
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return 0;
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}
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#ifdef DSEMUL_TRACE
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printk("dsemul %lx %lx\n", regs->cp0_epc, cpc);
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#endif
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pr_debug("dsemul %lx %lx\n", regs->cp0_epc, cpc);
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/*
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* The strategy is to push the instruction onto the user stack
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@ -149,9 +147,8 @@ int do_dsemulret(struct pt_regs *xcp)
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* emulating the branch delay instruction.
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*/
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#ifdef DSEMUL_TRACE
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printk("dsemulret\n");
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#endif
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pr_debug("dsemulret\n");
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if (__get_user(epc, &fr->epc)) { /* Saved EPC */
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/* This is not a good situation to be in */
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force_sig(SIGBUS, current);
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