drm/i915: Fix SKL cursor watermarks
Use intel_wm_plane_visible() to determine cursor visibility for SKL+
also. Previously SKL+ would check the actual visibility which now
conflicts with the assumptions in intel_legacy_cursor_update().
We also change SKL+ to compute the cursor watermarks based on the
unclipped cursor size, just as we do on all the other platforms.
Using the clipped size could now result in garbage results.
Testcase: igt/kms_chv_cursor_fail
Fixes: a5509abda4
("drm/i915: Fix legacy cursor vs. watermarks for ILK-BDW")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100195
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20170314151050.12194-2-ville.syrjala@linux.intel.com
Tested-by: Dorota Czaplejewicz <dorota.czaplejewicz@collabora.co.uk>
Tested-by: Jari Tahvanainen <jari.tahvanainen@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Acked-by: Ander Conselvan de Oliveira <conselvan2@gmail.com>
This commit is contained in:
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24304d8193
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93aa2a1c25
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@ -3361,19 +3361,29 @@ void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
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* Caller should take care of dividing & rounding off the value.
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* Caller should take care of dividing & rounding off the value.
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*/
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*/
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static uint32_t
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static uint32_t
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skl_plane_downscale_amount(const struct intel_plane_state *pstate)
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skl_plane_downscale_amount(const struct intel_crtc_state *cstate,
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const struct intel_plane_state *pstate)
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{
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{
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struct intel_plane *plane = to_intel_plane(pstate->base.plane);
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uint32_t downscale_h, downscale_w;
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uint32_t downscale_h, downscale_w;
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uint32_t src_w, src_h, dst_w, dst_h;
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uint32_t src_w, src_h, dst_w, dst_h;
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if (WARN_ON(!pstate->base.visible))
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if (WARN_ON(!intel_wm_plane_visible(cstate, pstate)))
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return DRM_PLANE_HELPER_NO_SCALING;
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return DRM_PLANE_HELPER_NO_SCALING;
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/* n.b., src is 16.16 fixed point, dst is whole integer */
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/* n.b., src is 16.16 fixed point, dst is whole integer */
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src_w = drm_rect_width(&pstate->base.src);
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if (plane->id == PLANE_CURSOR) {
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src_h = drm_rect_height(&pstate->base.src);
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src_w = pstate->base.src_w;
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dst_w = drm_rect_width(&pstate->base.dst);
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src_h = pstate->base.src_h;
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dst_h = drm_rect_height(&pstate->base.dst);
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dst_w = pstate->base.crtc_w;
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dst_h = pstate->base.crtc_h;
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} else {
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src_w = drm_rect_width(&pstate->base.src);
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src_h = drm_rect_height(&pstate->base.src);
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dst_w = drm_rect_width(&pstate->base.dst);
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dst_h = drm_rect_height(&pstate->base.dst);
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}
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if (drm_rotation_90_or_270(pstate->base.rotation))
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if (drm_rotation_90_or_270(pstate->base.rotation))
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swap(dst_w, dst_h);
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swap(dst_w, dst_h);
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@ -3389,6 +3399,7 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
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const struct drm_plane_state *pstate,
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const struct drm_plane_state *pstate,
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int y)
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int y)
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{
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{
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struct intel_plane *plane = to_intel_plane(pstate->plane);
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struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
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struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
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uint32_t down_scale_amount, data_rate;
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uint32_t down_scale_amount, data_rate;
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uint32_t width = 0, height = 0;
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uint32_t width = 0, height = 0;
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@ -3401,7 +3412,7 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
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fb = pstate->fb;
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fb = pstate->fb;
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format = fb->format->format;
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format = fb->format->format;
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if (pstate->plane->type == DRM_PLANE_TYPE_CURSOR)
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if (plane->id == PLANE_CURSOR)
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return 0;
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return 0;
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if (y && format != DRM_FORMAT_NV12)
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if (y && format != DRM_FORMAT_NV12)
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return 0;
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return 0;
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@ -3425,7 +3436,7 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
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data_rate = width * height * fb->format->cpp[0];
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data_rate = width * height * fb->format->cpp[0];
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}
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}
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down_scale_amount = skl_plane_downscale_amount(intel_pstate);
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down_scale_amount = skl_plane_downscale_amount(cstate, intel_pstate);
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return (uint64_t)data_rate * down_scale_amount >> 16;
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return (uint64_t)data_rate * down_scale_amount >> 16;
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}
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}
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@ -3717,7 +3728,7 @@ static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cst
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uint64_t pixel_rate;
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uint64_t pixel_rate;
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/* Shouldn't reach here on disabled planes... */
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/* Shouldn't reach here on disabled planes... */
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if (WARN_ON(!pstate->base.visible))
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if (WARN_ON(!intel_wm_plane_visible(cstate, pstate)))
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return 0;
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return 0;
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/*
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/*
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@ -3725,7 +3736,7 @@ static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cst
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* with additional adjustments for plane-specific scaling.
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* with additional adjustments for plane-specific scaling.
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*/
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*/
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adjusted_pixel_rate = cstate->pixel_rate;
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adjusted_pixel_rate = cstate->pixel_rate;
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downscale_amount = skl_plane_downscale_amount(pstate);
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downscale_amount = skl_plane_downscale_amount(cstate, pstate);
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pixel_rate = adjusted_pixel_rate * downscale_amount >> 16;
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pixel_rate = adjusted_pixel_rate * downscale_amount >> 16;
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WARN_ON(pixel_rate != clamp_t(uint32_t, pixel_rate, 0, ~0));
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WARN_ON(pixel_rate != clamp_t(uint32_t, pixel_rate, 0, ~0));
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@ -3742,6 +3753,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
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uint8_t *out_lines, /* out */
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uint8_t *out_lines, /* out */
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bool *enabled /* out */)
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bool *enabled /* out */)
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{
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{
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struct intel_plane *plane = to_intel_plane(intel_pstate->base.plane);
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struct drm_plane_state *pstate = &intel_pstate->base;
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struct drm_plane_state *pstate = &intel_pstate->base;
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struct drm_framebuffer *fb = pstate->fb;
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struct drm_framebuffer *fb = pstate->fb;
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uint32_t latency = dev_priv->wm.skl_latency[level];
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uint32_t latency = dev_priv->wm.skl_latency[level];
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@ -3761,7 +3773,8 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
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bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state);
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bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state);
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bool y_tiled, x_tiled;
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bool y_tiled, x_tiled;
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if (latency == 0 || !cstate->base.active || !intel_pstate->base.visible) {
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if (latency == 0 ||
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!intel_wm_plane_visible(cstate, intel_pstate)) {
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*enabled = false;
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*enabled = false;
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return 0;
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return 0;
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}
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}
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@ -3777,8 +3790,13 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
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if (apply_memory_bw_wa && x_tiled)
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if (apply_memory_bw_wa && x_tiled)
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latency += 15;
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latency += 15;
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width = drm_rect_width(&intel_pstate->base.src) >> 16;
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if (plane->id == PLANE_CURSOR) {
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height = drm_rect_height(&intel_pstate->base.src) >> 16;
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width = intel_pstate->base.crtc_w;
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height = intel_pstate->base.crtc_h;
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} else {
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width = drm_rect_width(&intel_pstate->base.src) >> 16;
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height = drm_rect_height(&intel_pstate->base.src) >> 16;
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}
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if (drm_rotation_90_or_270(pstate->rotation))
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if (drm_rotation_90_or_270(pstate->rotation))
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swap(width, height);
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swap(width, height);
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