From 93d90ad708b8da6efc0e487b66111aa9db7f70c7 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 14 Jan 2015 10:46:55 +1000 Subject: [PATCH] drm/nouveau/sec: separate from cipher (formerly crypt) Switch to NVIDIA's name for the device. The namespace of NVKM is being changed to nvkm_ instead of nouveau_, which will be used for the DRM part of the driver. This is being done in order to make it very clear as to what part of the driver a given symbol belongs to, and as a minor step towards splitting the DRM driver out to be able to stand on its own (for virt). Because there's already a large amount of churn here anyway, this is as good a time as any to also switch to NVIDIA's device and chipset naming to ease collaboration with them. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/include/nvif/class.h | 3 +- .../drm/nouveau/include/nvkm/core/device.h | 3 +- .../drm/nouveau/include/nvkm/engine/cipher.h | 4 + .../drm/nouveau/include/nvkm/engine/crypt.h | 7 -- .../gpu/drm/nouveau/include/nvkm/engine/sec.h | 4 + drivers/gpu/drm/nouveau/nvkm/engine/Kbuild | 3 +- .../gpu/drm/nouveau/nvkm/engine/cipher/Kbuild | 1 + .../nvkm/engine/{crypt => cipher}/nv84.c | 54 ++++----- .../gpu/drm/nouveau/nvkm/engine/crypt/Kbuild | 2 - .../gpu/drm/nouveau/nvkm/engine/device/base.c | 3 +- .../gpu/drm/nouveau/nvkm/engine/device/nv50.c | 21 ++-- .../gpu/drm/nouveau/nvkm/engine/fifo/nv84.c | 47 ++++---- .../gpu/drm/nouveau/nvkm/engine/sec/Kbuild | 1 + .../nvkm/engine/{crypt => sec}/fuc/nv98.fuc0s | 104 +++++++++--------- .../engine/{crypt => sec}/fuc/nv98.fuc0s.h | 54 ++++----- .../nouveau/nvkm/engine/{crypt => sec}/nv98.c | 48 ++++---- .../drm/nouveau/nvkm/subdev/devinit/nv84.c | 4 +- .../drm/nouveau/nvkm/subdev/devinit/nv98.c | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c | 4 +- drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv50.c | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv98.c | 2 +- .../gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c | 19 ++-- 22 files changed, 203 insertions(+), 189 deletions(-) create mode 100644 drivers/gpu/drm/nouveau/include/nvkm/engine/cipher.h delete mode 100644 drivers/gpu/drm/nouveau/include/nvkm/engine/crypt.h create mode 100644 drivers/gpu/drm/nouveau/include/nvkm/engine/sec.h create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/cipher/Kbuild rename drivers/gpu/drm/nouveau/nvkm/engine/{crypt => cipher}/nv84.c (80%) delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/crypt/Kbuild create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/sec/Kbuild rename drivers/gpu/drm/nouveau/nvkm/engine/{crypt => sec}/fuc/nv98.fuc0s (88%) rename drivers/gpu/drm/nouveau/nvkm/engine/{crypt => sec}/fuc/nv98.fuc0s.h (90%) rename drivers/gpu/drm/nouveau/nvkm/engine/{crypt => sec}/nv98.c (80%) diff --git a/drivers/gpu/drm/nouveau/include/nvif/class.h b/drivers/gpu/drm/nouveau/include/nvif/class.h index 6ed8ecca8dbf..d5da658d9d43 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/class.h +++ b/drivers/gpu/drm/nouveau/include/nvif/class.h @@ -126,7 +126,7 @@ struct nv_device_v0 { #define NV_DEVICE_V0_DISABLE_MPEG 0x0000000200000000ULL #define NV_DEVICE_V0_DISABLE_ME 0x0000000400000000ULL #define NV_DEVICE_V0_DISABLE_VP 0x0000000800000000ULL -#define NV_DEVICE_V0_DISABLE_CRYPT 0x0000001000000000ULL +#define NV_DEVICE_V0_DISABLE_CIPHER 0x0000001000000000ULL #define NV_DEVICE_V0_DISABLE_BSP 0x0000002000000000ULL #define NV_DEVICE_V0_DISABLE_PPP 0x0000004000000000ULL #define NV_DEVICE_V0_DISABLE_COPY0 0x0000008000000000ULL @@ -135,6 +135,7 @@ struct nv_device_v0 { #define NV_DEVICE_V0_DISABLE_VENC 0x0000040000000000ULL #define NV_DEVICE_V0_DISABLE_COPY2 0x0000080000000000ULL #define NV_DEVICE_V0_DISABLE_MSVLD 0x0000100000000000ULL +#define NV_DEVICE_V0_DISABLE_SEC 0x0000200000000000ULL __u64 disable; /* disable particular subsystems */ __u64 debug0; /* as above, but *internal* ids, and *NOT* ABI */ }; diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h index 7205d07f5cc9..cefa8774e11c 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h @@ -49,7 +49,7 @@ enum nv_subdev_type { NVDEV_ENGINE_MPEG, NVDEV_ENGINE_ME, NVDEV_ENGINE_VP, - NVDEV_ENGINE_CRYPT, + NVDEV_ENGINE_CIPHER, NVDEV_ENGINE_BSP, NVDEV_ENGINE_PPP, NVDEV_ENGINE_COPY0, @@ -60,6 +60,7 @@ enum nv_subdev_type { NVDEV_ENGINE_DISP, NVDEV_ENGINE_PERFMON, NVDEV_ENGINE_MSVLD, + NVDEV_ENGINE_SEC, NVDEV_SUBDEV_NR, }; diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/cipher.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/cipher.h new file mode 100644 index 000000000000..813bca367331 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/cipher.h @@ -0,0 +1,4 @@ +#ifndef __NVKM_CIPHER_H__ +#define __NVKM_CIPHER_H__ +extern struct nouveau_oclass nv84_cipher_oclass; +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/crypt.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/crypt.h deleted file mode 100644 index db975618e937..000000000000 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/crypt.h +++ /dev/null @@ -1,7 +0,0 @@ -#ifndef __NOUVEAU_CRYPT_H__ -#define __NOUVEAU_CRYPT_H__ - -extern struct nouveau_oclass nv84_crypt_oclass; -extern struct nouveau_oclass nv98_crypt_oclass; - -#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/sec.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/sec.h new file mode 100644 index 000000000000..32cd4cb0744c --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/sec.h @@ -0,0 +1,4 @@ +#ifndef __NVKM_SEC_H__ +#define __NVKM_SEC_H__ +extern struct nouveau_oclass nv98_sec_oclass; +#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild index b410eb1e2228..aad171d3cbcc 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild @@ -2,8 +2,8 @@ nvkm-y += nvkm/engine/falcon.o nvkm-y += nvkm/engine/xtensa.o include $(src)/nvkm/engine/bsp/Kbuild +include $(src)/nvkm/engine/cipher/Kbuild include $(src)/nvkm/engine/copy/Kbuild -include $(src)/nvkm/engine/crypt/Kbuild include $(src)/nvkm/engine/device/Kbuild include $(src)/nvkm/engine/disp/Kbuild include $(src)/nvkm/engine/dmaobj/Kbuild @@ -13,5 +13,6 @@ include $(src)/nvkm/engine/mpeg/Kbuild include $(src)/nvkm/engine/msvld/Kbuild include $(src)/nvkm/engine/perfmon/Kbuild include $(src)/nvkm/engine/ppp/Kbuild +include $(src)/nvkm/engine/sec/Kbuild include $(src)/nvkm/engine/software/Kbuild include $(src)/nvkm/engine/vp/Kbuild diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/cipher/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/cipher/Kbuild new file mode 100644 index 000000000000..07cc2150463b --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/cipher/Kbuild @@ -0,0 +1 @@ +nvkm-y += nvkm/engine/cipher/nv84.o diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/crypt/nv84.c b/drivers/gpu/drm/nouveau/nvkm/engine/cipher/nv84.c similarity index 80% rename from drivers/gpu/drm/nouveau/nvkm/engine/crypt/nv84.c rename to drivers/gpu/drm/nouveau/nvkm/engine/cipher/nv84.c index ea5c42f31791..d4ecd91ccbe6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/crypt/nv84.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/cipher/nv84.c @@ -31,9 +31,9 @@ #include #include -#include +#include -struct nv84_crypt_priv { +struct nv84_cipher_priv { struct nouveau_engine base; }; @@ -42,7 +42,7 @@ struct nv84_crypt_priv { ******************************************************************************/ static int -nv84_crypt_object_ctor(struct nouveau_object *parent, +nv84_cipher_object_ctor(struct nouveau_object *parent, struct nouveau_object *engine, struct nouveau_oclass *oclass, void *data, u32 size, struct nouveau_object **pobject) @@ -64,8 +64,8 @@ nv84_crypt_object_ctor(struct nouveau_object *parent, } static struct nouveau_ofuncs -nv84_crypt_ofuncs = { - .ctor = nv84_crypt_object_ctor, +nv84_cipher_ofuncs = { + .ctor = nv84_cipher_object_ctor, .dtor = _nouveau_gpuobj_dtor, .init = _nouveau_gpuobj_init, .fini = _nouveau_gpuobj_fini, @@ -74,18 +74,18 @@ nv84_crypt_ofuncs = { }; static struct nouveau_oclass -nv84_crypt_sclass[] = { - { 0x74c1, &nv84_crypt_ofuncs }, +nv84_cipher_sclass[] = { + { 0x74c1, &nv84_cipher_ofuncs }, {} }; /******************************************************************************* - * PCRYPT context + * PCIPHER context ******************************************************************************/ static struct nouveau_oclass -nv84_crypt_cclass = { - .handle = NV_ENGCTX(CRYPT, 0x84), +nv84_cipher_cclass = { + .handle = NV_ENGCTX(CIPHER, 0x84), .ofuncs = &(struct nouveau_ofuncs) { .ctor = _nouveau_engctx_ctor, .dtor = _nouveau_engctx_dtor, @@ -97,10 +97,10 @@ nv84_crypt_cclass = { }; /******************************************************************************* - * PCRYPT engine/subdev functions + * PCIPHER engine/subdev functions ******************************************************************************/ -static const struct nouveau_bitfield nv84_crypt_intr_mask[] = { +static const struct nouveau_bitfield nv84_cipher_intr_mask[] = { { 0x00000001, "INVALID_STATE" }, { 0x00000002, "ILLEGAL_MTHD" }, { 0x00000004, "ILLEGAL_CLASS" }, @@ -110,12 +110,12 @@ static const struct nouveau_bitfield nv84_crypt_intr_mask[] = { }; static void -nv84_crypt_intr(struct nouveau_subdev *subdev) +nv84_cipher_intr(struct nouveau_subdev *subdev) { struct nouveau_fifo *pfifo = nouveau_fifo(subdev); struct nouveau_engine *engine = nv_engine(subdev); struct nouveau_object *engctx; - struct nv84_crypt_priv *priv = (void *)subdev; + struct nv84_cipher_priv *priv = (void *)subdev; u32 stat = nv_rd32(priv, 0x102130); u32 mthd = nv_rd32(priv, 0x102190); u32 data = nv_rd32(priv, 0x102194); @@ -127,7 +127,7 @@ nv84_crypt_intr(struct nouveau_subdev *subdev) if (stat) { nv_error(priv, "%s", ""); - nouveau_bitfield_print(nv84_crypt_intr_mask, stat); + nouveau_bitfield_print(nv84_cipher_intr_mask, stat); pr_cont(" ch %d [0x%010llx %s] mthd 0x%04x data 0x%08x\n", chid, (u64)inst << 12, nouveau_client_name(engctx), mthd, data); @@ -140,30 +140,30 @@ nv84_crypt_intr(struct nouveau_subdev *subdev) } static int -nv84_crypt_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +nv84_cipher_ctor(struct nouveau_object *parent, struct nouveau_object *engine, struct nouveau_oclass *oclass, void *data, u32 size, struct nouveau_object **pobject) { - struct nv84_crypt_priv *priv; + struct nv84_cipher_priv *priv; int ret; ret = nouveau_engine_create(parent, engine, oclass, true, - "PCRYPT", "crypt", &priv); + "PCIPHER", "cipher", &priv); *pobject = nv_object(priv); if (ret) return ret; nv_subdev(priv)->unit = 0x00004000; - nv_subdev(priv)->intr = nv84_crypt_intr; - nv_engine(priv)->cclass = &nv84_crypt_cclass; - nv_engine(priv)->sclass = nv84_crypt_sclass; + nv_subdev(priv)->intr = nv84_cipher_intr; + nv_engine(priv)->cclass = &nv84_cipher_cclass; + nv_engine(priv)->sclass = nv84_cipher_sclass; return 0; } static int -nv84_crypt_init(struct nouveau_object *object) +nv84_cipher_init(struct nouveau_object *object) { - struct nv84_crypt_priv *priv = (void *)object; + struct nv84_cipher_priv *priv = (void *)object; int ret; ret = nouveau_engine_init(&priv->base); @@ -177,12 +177,12 @@ nv84_crypt_init(struct nouveau_object *object) } struct nouveau_oclass -nv84_crypt_oclass = { - .handle = NV_ENGINE(CRYPT, 0x84), +nv84_cipher_oclass = { + .handle = NV_ENGINE(CIPHER, 0x84), .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv84_crypt_ctor, + .ctor = nv84_cipher_ctor, .dtor = _nouveau_engine_dtor, - .init = nv84_crypt_init, + .init = nv84_cipher_init, .fini = _nouveau_engine_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/crypt/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/crypt/Kbuild deleted file mode 100644 index eaeafdf3bc81..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/crypt/Kbuild +++ /dev/null @@ -1,2 +0,0 @@ -nvkm-y += nvkm/engine/crypt/nv84.o -nvkm-y += nvkm/engine/crypt/nv98.o diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c index 7945bba5e794..fe269ef00355 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c @@ -232,7 +232,7 @@ static const u64 disable_map[] = { [NVDEV_ENGINE_MPEG] = NV_DEVICE_V0_DISABLE_MPEG, [NVDEV_ENGINE_ME] = NV_DEVICE_V0_DISABLE_ME, [NVDEV_ENGINE_VP] = NV_DEVICE_V0_DISABLE_VP, - [NVDEV_ENGINE_CRYPT] = NV_DEVICE_V0_DISABLE_CRYPT, + [NVDEV_ENGINE_CIPHER] = NV_DEVICE_V0_DISABLE_CIPHER, [NVDEV_ENGINE_BSP] = NV_DEVICE_V0_DISABLE_BSP, [NVDEV_ENGINE_PPP] = NV_DEVICE_V0_DISABLE_PPP, [NVDEV_ENGINE_COPY0] = NV_DEVICE_V0_DISABLE_COPY0, @@ -242,6 +242,7 @@ static const u64 disable_map[] = { [NVDEV_ENGINE_VENC] = NV_DEVICE_V0_DISABLE_VENC, [NVDEV_ENGINE_DISP] = NV_DEVICE_V0_DISABLE_DISP, [NVDEV_ENGINE_MSVLD] = NV_DEVICE_V0_DISABLE_MSVLD, + [NVDEV_ENGINE_SEC] = NV_DEVICE_V0_DISABLE_SEC, [NVDEV_SUBDEV_NR] = 0, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c index 90f0e23f582e..2fb06eb451f3 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c @@ -47,7 +47,8 @@ #include #include #include -#include +#include +#include #include #include #include @@ -109,7 +110,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; - device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass; + device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass; device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv84_disp_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; @@ -138,7 +139,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; - device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass; + device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass; device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv84_disp_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; @@ -167,7 +168,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; - device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass; + device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass; device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv84_disp_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; @@ -196,7 +197,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; - device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass; + device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass; device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; @@ -225,7 +226,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; - device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass; + device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass; device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; @@ -253,7 +254,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; - device->oclass[NVDEV_ENGINE_CRYPT ] = &nv98_crypt_oclass; + device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass; @@ -283,7 +284,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; - device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass; + device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass; device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nva0_disp_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; @@ -311,7 +312,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; - device->oclass[NVDEV_ENGINE_CRYPT ] = &nv98_crypt_oclass; + device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass; @@ -340,7 +341,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; - device->oclass[NVDEV_ENGINE_CRYPT ] = &nv98_crypt_oclass; + device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass; device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv84.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv84.c index 7183bf1d7f5b..392843991663 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv84.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv84.c @@ -55,15 +55,16 @@ nv84_fifo_context_attach(struct nouveau_object *parent, u32 addr; switch (nv_engidx(object->engine)) { - case NVDEV_ENGINE_SW : return 0; - case NVDEV_ENGINE_GR : addr = 0x0020; break; - case NVDEV_ENGINE_VP : addr = 0x0040; break; - case NVDEV_ENGINE_PPP : - case NVDEV_ENGINE_MPEG : addr = 0x0060; break; - case NVDEV_ENGINE_BSP : - case NVDEV_ENGINE_MSVLD: addr = 0x0080; break; - case NVDEV_ENGINE_CRYPT: addr = 0x00a0; break; - case NVDEV_ENGINE_COPY0: addr = 0x00c0; break; + case NVDEV_ENGINE_SW : return 0; + case NVDEV_ENGINE_GR : addr = 0x0020; break; + case NVDEV_ENGINE_VP : addr = 0x0040; break; + case NVDEV_ENGINE_PPP : + case NVDEV_ENGINE_MPEG : addr = 0x0060; break; + case NVDEV_ENGINE_BSP : + case NVDEV_ENGINE_MSVLD : addr = 0x0080; break; + case NVDEV_ENGINE_CIPHER: + case NVDEV_ENGINE_SEC : addr = 0x00a0; break; + case NVDEV_ENGINE_COPY0 : addr = 0x00c0; break; default: return -EINVAL; } @@ -92,15 +93,16 @@ nv84_fifo_context_detach(struct nouveau_object *parent, bool suspend, bool done; switch (nv_engidx(object->engine)) { - case NVDEV_ENGINE_SW : return 0; - case NVDEV_ENGINE_GR : engn = 0; addr = 0x0020; break; - case NVDEV_ENGINE_VP : engn = 3; addr = 0x0040; break; - case NVDEV_ENGINE_PPP : - case NVDEV_ENGINE_MPEG : engn = 1; addr = 0x0060; break; - case NVDEV_ENGINE_BSP : - case NVDEV_ENGINE_MSVLD: engn = 5; addr = 0x0080; break; - case NVDEV_ENGINE_CRYPT: engn = 4; addr = 0x00a0; break; - case NVDEV_ENGINE_COPY0: engn = 2; addr = 0x00c0; break; + case NVDEV_ENGINE_SW : return 0; + case NVDEV_ENGINE_GR : engn = 0; addr = 0x0020; break; + case NVDEV_ENGINE_VP : engn = 3; addr = 0x0040; break; + case NVDEV_ENGINE_PPP : + case NVDEV_ENGINE_MPEG : engn = 1; addr = 0x0060; break; + case NVDEV_ENGINE_BSP : + case NVDEV_ENGINE_MSVLD : engn = 5; addr = 0x0080; break; + case NVDEV_ENGINE_CIPHER: + case NVDEV_ENGINE_SEC : engn = 4; addr = 0x00a0; break; + case NVDEV_ENGINE_COPY0 : engn = 2; addr = 0x00c0; break; default: return -EINVAL; } @@ -147,7 +149,8 @@ nv84_fifo_object_attach(struct nouveau_object *parent, case NVDEV_ENGINE_ME : case NVDEV_ENGINE_COPY0 : context |= 0x00300000; break; case NVDEV_ENGINE_VP : context |= 0x00400000; break; - case NVDEV_ENGINE_CRYPT : + case NVDEV_ENGINE_CIPHER: + case NVDEV_ENGINE_SEC : case NVDEV_ENGINE_VIC : context |= 0x00500000; break; case NVDEV_ENGINE_BSP : case NVDEV_ENGINE_MSVLD : context |= 0x00600000; break; @@ -188,7 +191,8 @@ nv84_fifo_chan_ctor_dma(struct nouveau_object *parent, (1ULL << NVDEV_ENGINE_MPEG) | (1ULL << NVDEV_ENGINE_ME) | (1ULL << NVDEV_ENGINE_VP) | - (1ULL << NVDEV_ENGINE_CRYPT) | + (1ULL << NVDEV_ENGINE_CIPHER) | + (1ULL << NVDEV_ENGINE_SEC) | (1ULL << NVDEV_ENGINE_BSP) | (1ULL << NVDEV_ENGINE_MSVLD) | (1ULL << NVDEV_ENGINE_PPP) | @@ -262,7 +266,8 @@ nv84_fifo_chan_ctor_ind(struct nouveau_object *parent, (1ULL << NVDEV_ENGINE_MPEG) | (1ULL << NVDEV_ENGINE_ME) | (1ULL << NVDEV_ENGINE_VP) | - (1ULL << NVDEV_ENGINE_CRYPT) | + (1ULL << NVDEV_ENGINE_CIPHER) | + (1ULL << NVDEV_ENGINE_SEC) | (1ULL << NVDEV_ENGINE_BSP) | (1ULL << NVDEV_ENGINE_MSVLD) | (1ULL << NVDEV_ENGINE_PPP) | diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sec/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/sec/Kbuild new file mode 100644 index 000000000000..5ce7a5073c97 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sec/Kbuild @@ -0,0 +1 @@ +nvkm-y += nvkm/engine/sec/nv98.o diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/crypt/fuc/nv98.fuc0s b/drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/nv98.fuc0s similarity index 88% rename from drivers/gpu/drm/nouveau/nvkm/engine/crypt/fuc/nv98.fuc0s rename to drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/nv98.fuc0s index 629da02dc352..0b9e77782a57 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/crypt/fuc/nv98.fuc0s +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/nv98.fuc0s @@ -1,5 +1,5 @@ /* - * fuc microcode for nv98 pcrypt engine + * fuc microcode for nv98 psec engine * Copyright (C) 2010 Marcin Kościelnicki * * This program is free software; you can redistribute it and/or modify @@ -17,7 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -.section #nv98_pcrypt_data +.section #nv98_psec_data ctx_dma: ctx_dma_query: .b32 0 @@ -70,31 +70,31 @@ engine_cmd_dtable: .b32 #ctx_src_address_low + 0x20000 ~0xfffffff0 .b32 #ctx_dst_address_high + 0x20000 ~0xff .b32 #ctx_dst_address_low + 0x20000 ~0xfffffff0 -.b32 #crypt_cmd_mode + 0x00000 ~0xf -.b32 #crypt_cmd_length + 0x10000 ~0x0ffffff0 +.b32 #sec_cmd_mode + 0x00000 ~0xf +.b32 #sec_cmd_length + 0x10000 ~0x0ffffff0 .equ #engine_cmd_max 0xce .align 4 -crypt_dtable: -.b16 #crypt_copy_prep #crypt_do_inout -.b16 #crypt_store_prep #crypt_do_out -.b16 #crypt_ecb_e_prep #crypt_do_inout -.b16 #crypt_ecb_d_prep #crypt_do_inout -.b16 #crypt_cbc_e_prep #crypt_do_inout -.b16 #crypt_cbc_d_prep #crypt_do_inout -.b16 #crypt_pcbc_e_prep #crypt_do_inout -.b16 #crypt_pcbc_d_prep #crypt_do_inout -.b16 #crypt_cfb_e_prep #crypt_do_inout -.b16 #crypt_cfb_d_prep #crypt_do_inout -.b16 #crypt_ofb_prep #crypt_do_inout -.b16 #crypt_ctr_prep #crypt_do_inout -.b16 #crypt_cbc_mac_prep #crypt_do_in -.b16 #crypt_cmac_finish_complete_prep #crypt_do_in -.b16 #crypt_cmac_finish_partial_prep #crypt_do_in +sec_dtable: +.b16 #sec_copy_prep #sec_do_inout +.b16 #sec_store_prep #sec_do_out +.b16 #sec_ecb_e_prep #sec_do_inout +.b16 #sec_ecb_d_prep #sec_do_inout +.b16 #sec_cbc_e_prep #sec_do_inout +.b16 #sec_cbc_d_prep #sec_do_inout +.b16 #sec_pcbc_e_prep #sec_do_inout +.b16 #sec_pcbc_d_prep #sec_do_inout +.b16 #sec_cfb_e_prep #sec_do_inout +.b16 #sec_cfb_d_prep #sec_do_inout +.b16 #sec_ofb_prep #sec_do_inout +.b16 #sec_ctr_prep #sec_do_inout +.b16 #sec_cbc_mac_prep #sec_do_in +.b16 #sec_cmac_finish_complete_prep #sec_do_in +.b16 #sec_cmac_finish_partial_prep #sec_do_in .align 0x100 -.section #nv98_pcrypt_code +.section #nv98_psec_code // $r0 is always set to 0 in our code - this allows some space savings. clear b32 $r0 @@ -417,23 +417,23 @@ cmd_wrcache_flush: iowr I[$r2] $r3 ret -crypt_cmd_mode: +sec_cmd_mode: // if >= 0xf, INVALID_ENUM bset $flags $p1 or $r2 2 cmpu b32 $r3 0xf - bra nc #crypt_cmd_mode_return + bra nc #sec_cmd_mode_return bclr $flags $p1 st b32 D[$r0 + #ctx_mode] $r3 - crypt_cmd_mode_return: + sec_cmd_mode_return: ret -crypt_cmd_length: +sec_cmd_length: // nop if length == 0 cmpu b32 $r3 0 - bra e #crypt_cmd_mode_return + bra e #sec_cmd_mode_return // init key, IV cxset 3 @@ -471,11 +471,11 @@ crypt_cmd_length: shl b32 $r8 2 // run prep - ld b16 $r9 D[$r8 + #crypt_dtable] + ld b16 $r9 D[$r8 + #sec_dtable] call $r9 // do it - ld b16 $r9 D[$r8 + #crypt_dtable + 2] + ld b16 $r9 D[$r8 + #sec_dtable + 2] call $r9 cxset 1 xdwait @@ -509,25 +509,25 @@ crypt_cmd_length: ret -crypt_copy_prep: +sec_copy_prep: cs0begin 2 cxsin $c0 cxsout $c0 ret -crypt_store_prep: +sec_store_prep: cs0begin 1 cxsout $c6 ret -crypt_ecb_e_prep: +sec_ecb_e_prep: cs0begin 3 cxsin $c0 cenc $c0 $c0 cxsout $c0 ret -crypt_ecb_d_prep: +sec_ecb_d_prep: ckexp $c7 $c7 cs0begin 3 cxsin $c0 @@ -535,7 +535,7 @@ crypt_ecb_d_prep: cxsout $c0 ret -crypt_cbc_e_prep: +sec_cbc_e_prep: cs0begin 4 cxsin $c0 cxor $c6 $c0 @@ -543,7 +543,7 @@ crypt_cbc_e_prep: cxsout $c6 ret -crypt_cbc_d_prep: +sec_cbc_d_prep: ckexp $c7 $c7 cs0begin 5 cmov $c2 $c6 @@ -553,7 +553,7 @@ crypt_cbc_d_prep: cxsout $c0 ret -crypt_pcbc_e_prep: +sec_pcbc_e_prep: cs0begin 5 cxsin $c0 cxor $c6 $c0 @@ -562,7 +562,7 @@ crypt_pcbc_e_prep: cxor $c6 $c0 ret -crypt_pcbc_d_prep: +sec_pcbc_d_prep: ckexp $c7 $c7 cs0begin 5 cxsin $c0 @@ -572,7 +572,7 @@ crypt_pcbc_d_prep: cxor $c6 $c0 ret -crypt_cfb_e_prep: +sec_cfb_e_prep: cs0begin 4 cenc $c6 $c6 cxsin $c0 @@ -580,7 +580,7 @@ crypt_cfb_e_prep: cxsout $c6 ret -crypt_cfb_d_prep: +sec_cfb_d_prep: cs0begin 4 cenc $c0 $c6 cxsin $c6 @@ -588,7 +588,7 @@ crypt_cfb_d_prep: cxsout $c0 ret -crypt_ofb_prep: +sec_ofb_prep: cs0begin 4 cenc $c6 $c6 cxsin $c0 @@ -596,7 +596,7 @@ crypt_ofb_prep: cxsout $c0 ret -crypt_ctr_prep: +sec_ctr_prep: cs0begin 5 cenc $c1 $c6 cadd $c6 1 @@ -605,14 +605,14 @@ crypt_ctr_prep: cxsout $c0 ret -crypt_cbc_mac_prep: +sec_cbc_mac_prep: cs0begin 3 cxsin $c0 cxor $c6 $c0 cenc $c6 $c6 ret -crypt_cmac_finish_complete_prep: +sec_cmac_finish_complete_prep: cs0begin 7 cxsin $c0 cxor $c6 $c0 @@ -623,7 +623,7 @@ crypt_cmac_finish_complete_prep: cenc $c6 $c6 ret -crypt_cmac_finish_partial_prep: +sec_cmac_finish_partial_prep: cs0begin 8 cxsin $c0 cxor $c6 $c0 @@ -636,12 +636,12 @@ crypt_cmac_finish_partial_prep: ret // TODO -crypt_do_in: +sec_do_in: add b32 $r3 $r5 mov $xdbase $r4 mov $r9 #swap sethi $r9 0x20000 - crypt_do_in_loop: + sec_do_in_loop: xdld $r5 $r9 xdwait cxset 0x22 @@ -650,17 +650,17 @@ crypt_do_in: xdwait add b32 $r5 0x10 cmpu b32 $r5 $r3 - bra ne #crypt_do_in_loop + bra ne #sec_do_in_loop cxset 1 xdwait ret -crypt_do_out: +sec_do_out: add b32 $r3 $r7 mov $xdbase $r6 mov $r9 #swap sethi $r9 0x20000 - crypt_do_out_loop: + sec_do_out_loop: cs0exec 1 cxset 0x61 xdld $r7 $r9 @@ -669,14 +669,14 @@ crypt_do_out: xdwait add b32 $r7 0x10 cmpu b32 $r7 $r3 - bra ne #crypt_do_out_loop + bra ne #sec_do_out_loop ret -crypt_do_inout: +sec_do_inout: add b32 $r3 $r5 mov $r9 #swap sethi $r9 0x20000 - crypt_do_inout_loop: + sec_do_inout_loop: mov $xdbase $r4 xdld $r5 $r9 xdwait @@ -692,7 +692,7 @@ crypt_do_inout: add b32 $r5 0x10 add b32 $r7 0x10 cmpu b32 $r5 $r3 - bra ne #crypt_do_inout_loop + bra ne #sec_do_inout_loop ret .align 0x100 diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/crypt/fuc/nv98.fuc0s.h b/drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/nv98.fuc0s.h similarity index 90% rename from drivers/gpu/drm/nouveau/nvkm/engine/crypt/fuc/nv98.fuc0s.h rename to drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/nv98.fuc0s.h index 38676c74e6e0..f7e1e135b59b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/crypt/fuc/nv98.fuc0s.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/nv98.fuc0s.h @@ -1,4 +1,4 @@ -uint32_t nv98_pcrypt_data[] = { +uint32_t nv98_psec_data[] = { /* 0x0000: ctx_dma */ /* 0x0000: ctx_dma_query */ 0x00000000, @@ -103,7 +103,7 @@ uint32_t nv98_pcrypt_data[] = { 0xfffffff0, 0x00010285, 0xf000000f, -/* 0x0150: crypt_dtable */ +/* 0x0150: sec_dtable */ 0x04db0321, 0x04b1032f, 0x04db0339, @@ -150,7 +150,7 @@ uint32_t nv98_pcrypt_data[] = { 0x00000000, }; -uint32_t nv98_pcrypt_code[] = { +uint32_t nv98_psec_code[] = { 0x17f004bd, 0x0010fe35, 0xf10004fe, @@ -329,14 +329,14 @@ uint32_t nv98_pcrypt_code[] = { 0xbd220027, 0x0133f034, 0xf80023d0, -/* 0x0271: crypt_cmd_mode */ +/* 0x0271: sec_cmd_mode */ 0x0131f400, 0xb00225f0, 0x18f40f34, 0x0132f409, -/* 0x0283: crypt_cmd_mode_return */ +/* 0x0283: sec_cmd_mode_return */ 0xf80d0380, -/* 0x0285: crypt_cmd_length */ +/* 0x0285: sec_cmd_length */ 0x0034b000, 0xf4fb0bf4, 0x47f0033c, @@ -376,33 +376,33 @@ uint32_t nv98_pcrypt_code[] = { 0xf05047f0, 0x04fa0643, 0xf803f805, -/* 0x0321: crypt_copy_prep */ +/* 0x0321: sec_copy_prep */ 0x203cf500, 0x003cf594, 0x003cf588, -/* 0x032f: crypt_store_prep */ +/* 0x032f: sec_store_prep */ 0xf500f88c, 0xf594103c, 0xf88c063c, -/* 0x0339: crypt_ecb_e_prep */ +/* 0x0339: sec_ecb_e_prep */ 0x303cf500, 0x003cf594, 0x003cf588, 0x003cf5d0, -/* 0x034b: crypt_ecb_d_prep */ +/* 0x034b: sec_ecb_d_prep */ 0xf500f88c, 0xf5c8773c, 0xf594303c, 0xf588003c, 0xf5d4003c, 0xf88c003c, -/* 0x0361: crypt_cbc_e_prep */ +/* 0x0361: sec_cbc_e_prep */ 0x403cf500, 0x003cf594, 0x063cf588, 0x663cf5ac, 0x063cf5d0, -/* 0x0377: crypt_cbc_d_prep */ +/* 0x0377: sec_cbc_d_prep */ 0xf500f88c, 0xf5c8773c, 0xf594503c, @@ -411,14 +411,14 @@ uint32_t nv98_pcrypt_code[] = { 0xf5d4603c, 0xf5ac203c, 0xf88c003c, -/* 0x0395: crypt_pcbc_e_prep */ +/* 0x0395: sec_pcbc_e_prep */ 0x503cf500, 0x003cf594, 0x063cf588, 0x663cf5ac, 0x063cf5d0, 0x063cf58c, -/* 0x03af: crypt_pcbc_d_prep */ +/* 0x03af: sec_pcbc_d_prep */ 0xf500f8ac, 0xf5c8773c, 0xf594503c, @@ -427,26 +427,26 @@ uint32_t nv98_pcrypt_code[] = { 0xf5ac163c, 0xf58c063c, 0xf8ac063c, -/* 0x03cd: crypt_cfb_e_prep */ +/* 0x03cd: sec_cfb_e_prep */ 0x403cf500, 0x663cf594, 0x003cf5d0, 0x063cf588, 0x063cf5ac, -/* 0x03e3: crypt_cfb_d_prep */ +/* 0x03e3: sec_cfb_d_prep */ 0xf500f88c, 0xf594403c, 0xf5d0603c, 0xf588063c, 0xf5ac603c, 0xf88c003c, -/* 0x03f9: crypt_ofb_prep */ +/* 0x03f9: sec_ofb_prep */ 0x403cf500, 0x663cf594, 0x003cf5d0, 0x603cf588, 0x003cf5ac, -/* 0x040f: crypt_ctr_prep */ +/* 0x040f: sec_ctr_prep */ 0xf500f88c, 0xf594503c, 0xf5d0613c, @@ -454,12 +454,12 @@ uint32_t nv98_pcrypt_code[] = { 0xf588003c, 0xf5ac103c, 0xf88c003c, -/* 0x0429: crypt_cbc_mac_prep */ +/* 0x0429: sec_cbc_mac_prep */ 0x303cf500, 0x003cf594, 0x063cf588, 0x663cf5ac, -/* 0x043b: crypt_cmac_finish_complete_prep */ +/* 0x043b: sec_cmac_finish_complete_prep */ 0xf500f8d0, 0xf594703c, 0xf588003c, @@ -469,7 +469,7 @@ uint32_t nv98_pcrypt_code[] = { 0xf5bc003c, 0xf5ac063c, 0xf8d0663c, -/* 0x045d: crypt_cmac_finish_partial_prep */ +/* 0x045d: sec_cmac_finish_partial_prep */ 0x803cf500, 0x003cf594, 0x063cf588, @@ -479,12 +479,12 @@ uint32_t nv98_pcrypt_code[] = { 0x003cf5bc, 0x063cf5bc, 0x663cf5ac, -/* 0x0483: crypt_do_in */ +/* 0x0483: sec_do_in */ 0xbb00f8d0, 0x47fe0035, 0x8097f100, 0x0293f000, -/* 0x0490: crypt_do_in_loop */ +/* 0x0490: sec_do_in_loop */ 0xf80559fa, 0x223cf403, 0xf50609fa, @@ -493,11 +493,11 @@ uint32_t nv98_pcrypt_code[] = { 0xf40453b8, 0x3cf4e91b, 0xf803f801, -/* 0x04b1: crypt_do_out */ +/* 0x04b1: sec_do_out */ 0x0037bb00, 0xf10067fe, 0xf0008097, -/* 0x04be: crypt_do_out_loop */ +/* 0x04be: sec_do_out_loop */ 0x3cf50293, 0x3cf49810, 0x0579fa61, @@ -505,11 +505,11 @@ uint32_t nv98_pcrypt_code[] = { 0x03f8013c, 0xb81070b6, 0x1bf40473, -/* 0x04db: crypt_do_inout */ +/* 0x04db: sec_do_inout */ 0xbb00f8e8, 0x97f10035, 0x93f00080, -/* 0x04e5: crypt_do_inout_loop */ +/* 0x04e5: sec_do_inout_loop */ 0x0047fe02, 0xf80559fa, 0x213cf403, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/crypt/nv98.c b/drivers/gpu/drm/nouveau/nvkm/engine/sec/nv98.c similarity index 80% rename from drivers/gpu/drm/nouveau/nvkm/engine/crypt/nv98.c rename to drivers/gpu/drm/nouveau/nvkm/engine/sec/nv98.c index e0838c46ec17..10d0d1ff2694 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/crypt/nv98.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sec/nv98.c @@ -32,11 +32,11 @@ #include #include -#include +#include #include "fuc/nv98.fuc0s.h" -struct nv98_crypt_priv { +struct nv98_sec_priv { struct nouveau_falcon base; }; @@ -45,18 +45,18 @@ struct nv98_crypt_priv { ******************************************************************************/ static struct nouveau_oclass -nv98_crypt_sclass[] = { +nv98_sec_sclass[] = { { 0x88b4, &nouveau_object_ofuncs }, {}, }; /******************************************************************************* - * PCRYPT context + * PSEC context ******************************************************************************/ static struct nouveau_oclass -nv98_crypt_cclass = { - .handle = NV_ENGCTX(CRYPT, 0x98), +nv98_sec_cclass = { + .handle = NV_ENGCTX(SEC, 0x98), .ofuncs = &(struct nouveau_ofuncs) { .ctor = _nouveau_falcon_context_ctor, .dtor = _nouveau_falcon_context_dtor, @@ -68,10 +68,10 @@ nv98_crypt_cclass = { }; /******************************************************************************* - * PCRYPT engine/subdev functions + * PSEC engine/subdev functions ******************************************************************************/ -static const struct nouveau_enum nv98_crypt_isr_error_name[] = { +static const struct nouveau_enum nv98_sec_isr_error_name[] = { { 0x0000, "ILLEGAL_MTHD" }, { 0x0001, "INVALID_BITFIELD" }, { 0x0002, "INVALID_ENUM" }, @@ -80,12 +80,12 @@ static const struct nouveau_enum nv98_crypt_isr_error_name[] = { }; static void -nv98_crypt_intr(struct nouveau_subdev *subdev) +nv98_sec_intr(struct nouveau_subdev *subdev) { struct nouveau_fifo *pfifo = nouveau_fifo(subdev); struct nouveau_engine *engine = nv_engine(subdev); struct nouveau_object *engctx; - struct nv98_crypt_priv *priv = (void *)subdev; + struct nv98_sec_priv *priv = (void *)subdev; u32 disp = nv_rd32(priv, 0x08701c); u32 stat = nv_rd32(priv, 0x087008) & disp & ~(disp >> 16); u32 inst = nv_rd32(priv, 0x087050) & 0x3fffffff; @@ -101,7 +101,7 @@ nv98_crypt_intr(struct nouveau_subdev *subdev) if (stat & 0x00000040) { nv_error(priv, "DISPATCH_ERROR ["); - nouveau_enum_print(nv98_crypt_isr_error_name, ssta); + nouveau_enum_print(nv98_sec_isr_error_name, ssta); pr_cont("] ch %d [0x%010llx %s] subc %d mthd 0x%04x data 0x%08x\n", chid, (u64)inst << 12, nouveau_client_name(engctx), subc, mthd, data); @@ -118,35 +118,35 @@ nv98_crypt_intr(struct nouveau_subdev *subdev) } static int -nv98_crypt_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +nv98_sec_ctor(struct nouveau_object *parent, struct nouveau_object *engine, struct nouveau_oclass *oclass, void *data, u32 size, struct nouveau_object **pobject) { - struct nv98_crypt_priv *priv; + struct nv98_sec_priv *priv; int ret; ret = nouveau_falcon_create(parent, engine, oclass, 0x087000, true, - "PCRYPT", "crypt", &priv); + "PSEC", "sec", &priv); *pobject = nv_object(priv); if (ret) return ret; nv_subdev(priv)->unit = 0x00004000; - nv_subdev(priv)->intr = nv98_crypt_intr; - nv_engine(priv)->cclass = &nv98_crypt_cclass; - nv_engine(priv)->sclass = nv98_crypt_sclass; - nv_falcon(priv)->code.data = nv98_pcrypt_code; - nv_falcon(priv)->code.size = sizeof(nv98_pcrypt_code); - nv_falcon(priv)->data.data = nv98_pcrypt_data; - nv_falcon(priv)->data.size = sizeof(nv98_pcrypt_data); + nv_subdev(priv)->intr = nv98_sec_intr; + nv_engine(priv)->cclass = &nv98_sec_cclass; + nv_engine(priv)->sclass = nv98_sec_sclass; + nv_falcon(priv)->code.data = nv98_psec_code; + nv_falcon(priv)->code.size = sizeof(nv98_psec_code); + nv_falcon(priv)->data.data = nv98_psec_data; + nv_falcon(priv)->data.size = sizeof(nv98_psec_data); return 0; } struct nouveau_oclass -nv98_crypt_oclass = { - .handle = NV_ENGINE(CRYPT, 0x98), +nv98_sec_oclass = { + .handle = NV_ENGINE(SEC, 0x98), .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv98_crypt_ctor, + .ctor = nv98_sec_ctor, .dtor = _nouveau_falcon_dtor, .init = _nouveau_falcon_init, .fini = _nouveau_falcon_fini, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv84.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv84.c index a7c80ded77cd..c4f4c158dc1b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv84.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv84.c @@ -36,7 +36,7 @@ nv84_devinit_disable(struct nouveau_devinit *devinit) disable |= (1ULL << NVDEV_ENGINE_MPEG); disable |= (1ULL << NVDEV_ENGINE_VP); disable |= (1ULL << NVDEV_ENGINE_BSP); - disable |= (1ULL << NVDEV_ENGINE_CRYPT); + disable |= (1ULL << NVDEV_ENGINE_CIPHER); } if (!(r00154c & 0x00000004)) @@ -44,7 +44,7 @@ nv84_devinit_disable(struct nouveau_devinit *devinit) if (!(r00154c & 0x00000020)) disable |= (1ULL << NVDEV_ENGINE_BSP); if (!(r00154c & 0x00000040)) - disable |= (1ULL << NVDEV_ENGINE_CRYPT); + disable |= (1ULL << NVDEV_ENGINE_CIPHER); return disable; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv98.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv98.c index 820f069fbaac..b27984bbfebb 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv98.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv98.c @@ -43,7 +43,7 @@ nv98_devinit_disable(struct nouveau_devinit *devinit) if (!(r00154c & 0x00000020)) disable |= (1ULL << NVDEV_ENGINE_MSVLD); if (!(r00154c & 0x00000040)) - disable |= (1ULL << NVDEV_ENGINE_CRYPT); + disable |= (1ULL << NVDEV_ENGINE_SEC); return disable; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c index df07c046213e..31c90dbea579 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c @@ -124,7 +124,7 @@ static const struct nouveau_enum vm_engine[] = { { 0x00000008, "PPPP", NULL, NVDEV_ENGINE_PPP }, { 0x00000008, "PMPEG", NULL, NVDEV_ENGINE_MPEG }, { 0x00000009, "PBSP", NULL, NVDEV_ENGINE_BSP }, - { 0x0000000a, "PCRYPT", NULL, NVDEV_ENGINE_CRYPT }, + { 0x0000000a, "PCRYPT", NULL, NVDEV_ENGINE_CIPHER }, { 0x0000000b, "PCOUNTER", NULL }, { 0x0000000c, "SEMAPHORE_BG", NULL }, { 0x0000000d, "PCOPY", NULL, NVDEV_ENGINE_COPY0 }, @@ -192,6 +192,8 @@ nv50_fb_intr(struct nouveau_subdev *subdev) /*XXX: clean this up */ if (!engine && en->data2 == NVDEV_ENGINE_BSP) engine = nouveau_engine(subdev, NVDEV_ENGINE_MSVLD); + if (!engine && en->data2 == NVDEV_ENGINE_CIPHER) + engine = nouveau_engine(subdev, NVDEV_ENGINE_SEC); if (engine) { engctx = nouveau_engctx_get(engine, chan); if (engctx) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv50.c index 9ca93e2718f7..9100f2875636 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv50.c @@ -30,7 +30,7 @@ nv50_mc_intr[] = { { 0x00000001, NVDEV_ENGINE_MPEG }, { 0x00000100, NVDEV_ENGINE_FIFO }, { 0x00001000, NVDEV_ENGINE_GR }, - { 0x00004000, NVDEV_ENGINE_CRYPT }, /* NV84- */ + { 0x00004000, NVDEV_ENGINE_CIPHER }, /* NV84- */ { 0x00008000, NVDEV_ENGINE_BSP }, /* NV84- */ { 0x00020000, NVDEV_ENGINE_VP }, /* NV84- */ { 0x00100000, NVDEV_SUBDEV_TIMER }, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv98.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv98.c index bb1346f6fa12..17ea7e74ed28 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv98.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv98.c @@ -30,7 +30,7 @@ nv98_mc_intr[] = { { 0x00000001, NVDEV_ENGINE_PPP }, { 0x00000100, NVDEV_ENGINE_FIFO }, { 0x00001000, NVDEV_ENGINE_GR }, - { 0x00004000, NVDEV_ENGINE_CRYPT }, /* NV84:NVA3 */ + { 0x00004000, NVDEV_ENGINE_SEC }, /* NV84:NVA3 */ { 0x00008000, NVDEV_ENGINE_MSVLD }, { 0x00020000, NVDEV_ENGINE_VP }, { 0x00040000, NVDEV_SUBDEV_PMU }, /* NVA3:NVC0 */ diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c index eabf2bab1d10..9a8cbfb0718e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c @@ -171,15 +171,16 @@ nv50_vm_flush(struct nouveau_vm *vm) } switch (i) { - case NVDEV_ENGINE_GR : vme = 0x00; break; - case NVDEV_ENGINE_VP : vme = 0x01; break; - case NVDEV_SUBDEV_BAR : vme = 0x06; break; - case NVDEV_ENGINE_PPP : - case NVDEV_ENGINE_MPEG : vme = 0x08; break; - case NVDEV_ENGINE_BSP : - case NVDEV_ENGINE_MSVLD: vme = 0x09; break; - case NVDEV_ENGINE_CRYPT: vme = 0x0a; break; - case NVDEV_ENGINE_COPY0: vme = 0x0d; break; + case NVDEV_ENGINE_GR : vme = 0x00; break; + case NVDEV_ENGINE_VP : vme = 0x01; break; + case NVDEV_SUBDEV_BAR : vme = 0x06; break; + case NVDEV_ENGINE_PPP : + case NVDEV_ENGINE_MPEG : vme = 0x08; break; + case NVDEV_ENGINE_BSP : + case NVDEV_ENGINE_MSVLD : vme = 0x09; break; + case NVDEV_ENGINE_CIPHER: + case NVDEV_ENGINE_SEC : vme = 0x0a; break; + case NVDEV_ENGINE_COPY0 : vme = 0x0d; break; default: continue; }